MC68EC060RC50 Freescale Semiconductor, MC68EC060RC50 Datasheet - Page 91

• Manufacturer Part Number: MC68EC060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Memory Management Unit
4.2.6.2 SUPERVISOR ONLY. A second mechanism protects supervisor programs and data
without requiring segmenting of the logical address space into supervisor and user address
spaces. Page descriptors contain S-bits to protect areas of memory from access by user
programs. When a table search for a user access encounters an S-bit set in a page descrip-
tor, the table search ends, and an access error exception is taken immediately for data
accesses, or when the instruction is needed for instruction accesses. The S-bit can be used
to protect one or more pages from user program access. Supervisor and user mode
accesses can share descriptors by using indirect descriptors or by sharing tables. The entire
user and supervisor address spaces can be mapped together by loading the same root
pointer address into both the SRP and URP registers.
4.2.6.3 WRITE PROTECT. The MC68060 provides write protection independent of other
protection mechanisms. All table and page descriptors contain W-bits to protect areas of
memory from write accesses of any kind, including supervisor writes. On a read-only
access, if the ATC misses, and a W-bit (write-protect) is set in one or more of the table
descriptors, the table search completes normally and the ATC is loaded with the internal W-
bit set. Subsequent read-only accesses are allowed, but a subsequent write or read-modify-
write access to that address will immediately take the access error exception as a write-pro-
tect violation. The ATC entry and the related translation table entries are unchanged. On a
write or read-modify-write access, if the ATC misses and a W-bit is found set in any table
descriptor, the table search will terminate immediately and the access error exception is
taken. In this case the ATC is not loaded, and the translation table history bits (U and M) for
that descriptor are not updated. The W-bit can be used to protect the entire area of memory
defined by a branch of the translation table or protect only one or more pages from write
accesses. Figure 4-17 illustrates a memory map of the logical address space organized to
use supervisor-only and write-protect bits for protection. Figure 4-18 illustrates an example
translation table for this technique.
SUPERVISOR AND USER SPACE
THIS AREA IS SUPERVISOR ONLY, READ-ONLY
THIS AREA IS SUPERVISOR ONLY, READ/WRITE
THIS AREA IS SUPERVISOR OR USER, READ-ONLY
THIS AREA IS SUPERVISOR OR USER, READ/WRITE
Figure 4-17. Logical Address Map with Shared
Supervisor and User Address Spaces
4-22
M68060 USER’S MANUAL
MOTOROLA