MC68EC060RC50 Freescale Semiconductor, MC68EC060RC50 Datasheet - Page 376

• Manufacturer Part Number: MC68EC060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MC68060 Software Package
C.3.2.2.2 System-Supplied Floating-Point Arithmetic Exception Handler Call-Outs.
The call-outs _real_bsun, _real_snan, _real_operr, _real_ovfl, _real_unfl, _real_dz,
_real_inex are needed only if the system turns on the floating-point exceptions via the float-
ing-point control register (FPCR) exception enable byte. These call-outs point to the arith-
metic handlers that must be supplied for IEEE trap enabled operation. Documentation for
these handlers are fully explained in Section 6 Floating-Point Unit . Additional information
on how these call-outs are reached is found in C.3.2.3 Bypassing Module-Supplied Float-
ing-Point Arithmetic Handlers and C.3.2.4 Exceptions During Emulation .
C.3.2.2.3 Exception-Related Call-Outs. When in the process of emulating any of the float-
ing-point exception handlers, there are conditions that require the M68060SP to emulate an
access error, trace, or trap exception. The M68060SP does so by cleaning up the stack to
the conditions prior to executing the exception handler, converting the original stack frame
to the appropriate stack frame and then branching to those system-supplied exception han-
dlers.
The call-outs _real_access, _real_trace, and _real_trap are defined to provide the system
integrator a choice of either having the module point directly to the actual access error, trace
and trap exception handlers or to an alternate routine that would calculate the exception
handler address from the vector table prior to jumping to actual handlers. The direct imple-
mentation is ideal for systems that do not anticipate any changes to the vector table, and for
which performance is more critical. The indirect approach of consulting the vector table is
more accurate in that if the instruction were implemented, the actual handler’s address is
fetched from the appropriate vector table entry before branching there.
C.3.2.2.4 Exit Point Call-Outs. The _fpsp_done call-out is provided as a means for the
system to do any clean-up, if necessary, before executing the RTE instruction to return to
normal instruction execution. All the supplied floating-point handlers will either branch to this
call-out or exit through the call-outs _real_fline, _real_fpu_disabled, _real_trace, _real_trap,
_real_access, _real_bsun, _real_snan, _real_operr, _real_ovfl, _real_unfl, _real_dz, and
_real_inex exit points.
C.3.2.3 BYPASSING MODULE-SUPPLIED FLOATING-POINT ARITHMETIC
HANDLERS. A system that does not require full IEEE trap enabled exception compliance
or does not require the services of the exceptional operand, may choose to bypass the
_fpsp_{ovfl,unfl,snan,operr,dz,inex} entry points. To better assess whether or not to write a
customized floating-point arithmetic handler, it is important to know what the processor
hardware does and what the M68060SP handlers do individually.
The term “opclass” is used in the following paragraphs. An opclass zero instruction refers to
a floating-point general instruction whose source operand(s) and destination operand are all
floating-point data registers (no operands in memory). An opclass two instruction refers to a
floating-point general instruction in which one source operand is in memory or an integer
data register, but the destination is a floating-point data register. An opclass three instruction
refers to an FMOVE instruction that has a memory or integer data register destination.
MOTOROLA
M68060 USER’S MANUAL
C-15