MC68EC060RC50 Freescale Semiconductor, MC68EC060RC50 Datasheet - Page 122

• Manufacturer Part Number: MC68EC060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Floating-Point Unit
The processor supports four rounding modes specified by the IEEE 754 standard. These
modes are round to nearest (RN), round toward zero (RZ), round toward plus infinity (RP),
and round toward minus infinity (RM). The RP and RM modes are directed rounding modes
that are useful in interval arithmetic. Rounding is accomplished through the intermediate
result. Single-precision results are rounded to a 24-bit boundary; double-precision results
are rounded to a 53-bit boundary; and extended-precision results are rounded to a 64-bit
boundary. Table 6-1 lists the encoding for the rounding mode. Table 6-2 lists the encoding
for rounding precision.
6.1.3 Floating-Point Status Register (FPSR)
The FPSR (see Figure 6-2) contains a floating-point condition code byte (FPCC), a quotient
byte, a floating-point exception status byte (EXC), and a floating-point accrued exception
byte (AEXC). The user can read or write to all defined bits in the FPSR. Execution of most
floating-point instructions modifies this register. The reset function or a restore operation of
the null state clears the FPSR. Floating-point conditional operations are not guaranteed if
the FPSR is written directly, because the FPSR is only valid as a result of a floating-point
instruction.
6-4
BSUN
15
SNAN OPERR
14
13
Figure 6-3. Floating-Point Control Register Format
EXCEPTION ENABLE
OVFL
12
UNFL
11
0
0
1
1
0
0
1
1
Encoding
Encoding
Table 6-2. PREC Encoding
10
DZ
Table 6-1. RND Encoding
M68060 USER’S MANUAL
INEX2 INEX1
9
0
1
0
1
0
1
0
1
8
Toward Minus Infinity (RM)
Toward Plus Infinity (RP)
7
Rounding Precision
PREC
Toward Zero (RZ)
Rounding Mode
To Nearest (RN)
Double (D)
Extend (X)
Undefined
Single (S)
6
5
RND
MODE CONTROL
4
3
ROUNDING MODE
ROUNDING PRECISION
INEXACT DECIMAL INPUT
INEXACT OPERATION
DIVIDE-BY-ZERO
UNDERFLOW
OVERFLOW
OPERAND ERROR
SIGNALING NOT-A-NUMBER
BRANCH/SET ON UNORDERED
2
0
1
MOTOROLA
0