MC68EC060RC50 Freescale Semiconductor, MC68EC060RC50 Datasheet - Page 325

• Manufacturer Part Number: MC68EC060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Applications Information
used to install the M68040FPSP must be removed and then replaced with software that
installs the M68060SP. Be aware that the M68060SP and the M68040FPSP share many
vector table entries and that the M68040FPSP does not work properly with the MC68060.
The M68060SP must be installed before any of the new unimplemented instructions and
unimplemented effective addresses are encountered.
11.1.2.1.4 Cache Control Register (CACR) (MOVEC of CACR). As with the MC68040,
the MC68060 requires that the instruction and data caches be invalidated prior to their use.
In addition to this, the MC68060 requires that the branch cache be invalidated prior to its
use. The branch cache is cleared via the MOVEC to CACR instruction.
Care must be taken whenever the CACR is referenced in existing MC68040 code. Since the
MC68040 does not implement the new CACR bits, and existing MC68040 code may refer-
ence the CACR, the new CACR bits are likely to be cleared by MC68040-code CACR writes.
If this occurs, the branch cache is retained and the four-deep store buffer is disabled.
Although this would not adversely affect proper operation, it significantly degrades
MC68060 performance.
11.1.2.1.5 Resource Checking (Access Error Handler). Many systems use the access
error handler at some time after reset to check for the existence of I/O devices or memory.
Existing MC68040 systems already have to deal with the restart nature of the MC68040.
However, the stack frame generated by the MC68040 is significantly different from that of
the MC68060. Resource checking software that relies on the stack size information must be
modified appropriately.
When upgrading to the MC68060 from an existing MC68030 or MC68020 system, porting
resource checking software may be problematic because the continuation architecture
(MC68030 and MC68020) allows an operand read bus error to be ignored and not re-run
the offending instruction, but a restart machine such as the MC68060 has no provisions for
doing so. A possible work-around for this is to either increment the stacked program counter
(PC) prior to the RTE, or to use a NOP-RESOURCE_WRITE-NOP in place of the
RESOURCE_READ, in imprecise exception mode, to poke at the possible resource area.
11.1.2.2 VIRTUAL MEMORY SOFTWARE. The MC68060 fully supports virtual memory.
There are some slight changes that need to be made to support the MC68060 virtual mem-
ory. The following paragraphs outline issues that need to be addressed in relation to virtual
memory support.
11.1.2.2.1 Translation Control Register (MOVEC of TCR) . The TCR is accessed via the
MOVEC instruction, as with the MC68040. However, the TCR has newly defined bits. Since
these new bits need to be cleared in normal operating mode anyway, no additional work is
needed.
When the MC68040 emerges from reset, the default translation is cacheable write-through,
UPAx=0, and no write protect. The MC68060 provides a means for modifying these default
translation parameters. There are new bits in the MC68060 TCR to define the default trans-
lation.
MOTOROLA
M68060 USER’S MANUAL
11-3