PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 63

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

NXP Semiconductors
Volume 1 of 1
Table 37: VIP and FGPI Timing
PNX15XX_PNX952X_SER_N_4
Product data sheet
Symbol
F
F
T
T
VIP
FGPI
SU-CLK
H-CLK
Parameter
VDI_CLK1 frequency
VDI_CLK2 frequency
Input setup time
Input hold time
7.5 VIP and FGPI Interfaces
[36-1]
[36-2]
[36-3]
[36-4]
[36-5]
[37-1]
[37-2]
[37-3]
[37-4]
Figure 12: QVCP and FGPO I/O Timing
Figure 13: VIP and FGPI I/O Timing
See timing measurement conditions
Timing applies when the data is output on a positive or a negative edge in double edge clock
mode, see
3. If the VDO_CLK[1,2] is inverted internally then the timing applies to the negative edge.
Timing applies for VDO_D[29], FGPO_REC_SYNC and FGPO_BUF_SYNC. VDO_D[29]
and FGPO_BUF_SYNC. These inputs are assumed asynchronous.
Maximum frequency may get reduced by the wide spread of propagation delay depending
on the application needs, i.e. input setup/hold time requirements of the receiving device.
Notes:
1. Timing applies whether the clock is external or internal.
2. Timing applies whether the data is output on a positive or a negative edge.
3. See timing measurement conditions
Rev. 4.0 — 03 December 2007
Table 1 on page
FGPO_REC_SYNC
FGPO_BUF_SYNC
FGPO_REC_SYNC
FGPO_BUF_SYNC
VDI_D[33:0]
VDI_V[1:0]
VDO_D[34:0]
VDI_CLK
VDO_D[29]
VDO_CLK
VDO_CLK
3-114.
Figure
Figure
Min
3
2
T
SU-CLK
12.
T
SU-CLK
13.
PNX15xx/952x Series
Chapter 1: Integrated Circuit Data
valid
Max
81
100
valid
T
H-CLK
T
T
CLK-DV
H-CLK
valid
Units
MHz
MHz
ns
ns
© NXP B.V. 2007. All rights reserved.
Notes
1, 2, 3
1, 2, 3
1-63