PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 326

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
2.5.1 Halting and Unhalting
2.5.2 MMIO Directed Halt
2.5.3 Auto Halt
There are three different ways in which halting can be achieved:
In Halt mode, the DDR devices are sent into self-refresh mode.
MMIO register IP_2031_CTL, field HALT can be written with a ‘1’ to indicate a request
for halting. Write a ‘0’ to this field to indicate a request for taking the DDR controller
out of halt mode. Direct Halt directives are meant to be used when the PNX15xx/952x
Series system is sent to sleep and therefore no request is supposed to happen on the
MTL port. Direct Halt un-halt command is also used/required when changing the
clock frequency of the DDR interface.
Software must wait for a time period equal to a minimum of 256 DDR SDRAM
Controller clocks before clocks are changed or turned off.
The DDR SDRAM Controller can turn itself in halt mode when it has observed a
certain period of inactivity. By programming the MMIO registers HALT_COUNT and
CTL a period can be defined and automatic halting can be activated. The DDR
controller will automatically unhalt when a new MTL memory request is presented to
one of its input ports. To ensure the IP_2031 can detect these MTL memory requests,
the DDR controller clock inputs need to be turned on during auto halt (or at least have
1. By means of writing the halt register-field of a software programmable MMIO
2. Telling the DDR SDRAM Controller to go into halt mode automatically after a
register.
certain period of inactivity.
Rev. 4.0 — 03 December 2007
PNX15xx/952x Series
Chapter 9: DDR Controller
© NXP B.V. 2007. All rights reserved.
9-326