PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 60

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

NXP Semiconductors
Volume 1 of 1
Table 33: DDR DRAM Interface Timing
Table 34: PCI Bus Timing
PNX15XX_PNX952X_SER_N_4
Product data sheet
Symbol
T
T
T
Symbol
T
T
T
T
T
T
T
T
T
T
T
on-PCI
rst-off-PCI
iskew-dqs
is-dq
ih-dq
clock
clock-low
clock-high
val-PCI (Bus)
val-PCI (ptp)
Off-PCI
su-PCI
su-PCI (ptp)
h-PCI
Parameter
Maximum input skew supported
(when reading from DDR SDRAM)
Input setup time for MM_DQ
(when reading from DDR SDRAM)
Input hold time for MM_DQ
(when reading from DDR SDRAM)
Parameter
Clock cycle time
Clock Low time
Clock High time
Clk to signal valid delay, bus signals
Clk to signal valid delay, point-to-point signals
Float to active delay
Active to float delay
Input setup time to CLK - bus signals
Input setup time to CLK - point-to-point signals
Input hold time from CLK
Reset active to output float delay
7.3 PCI Bus Interface
[33-1]
[33-2]
[33-3]
[33-4]
[33-5]
[33-6]
[34-1]
[34-2]
[34-3]
[34-4]
[34-5]
[34-6]
Notes:
1. Command signals include MM_CKE_N[1:0], MM_CS[1:0]_N, MM_RAS_N, MM_CAS_N,
MM_WE_N, MM_BA[1:0] and MM_A[13:0] signals.
2. Times are measured w.r.t. the positive edge of MM_CLK and the crossing point of
MM_CLK and MM_CLK_N.
3. Refer to
4. Times are measured w.r.t. the corresponding edge of MM_DQS[3:0], i.e. MM_DQS[0] if
the DDR device is organized in x32, or respectively MM_DQ[31:24], MM_DQ[23:16],
MM_DQ[15:8] and MM_DQ[7:0] (when applicable) if the DDR devices organized in x8 or x16
are used.
5. These timings allow a 250 ps maximum board level skew for MM_CK. MM_CK_N,
MM_DQS[3:0] and MM_DQ[31:0] for a 200 MHz operating frequency (i.e. DDR400).
Notes:
1. See the timing measurement conditions in
2. Minimum times are measured at the package pin with the load circuit shown in
Maximum times are measured with the load circuits shown in
3. PCI_REQ_N and PCI_GNT_N are point-to-point signals and have different input setup
times. All other signals are bused.
4. See the timing measurement conditions in
5. All output drivers are floated when PCI_RST (PCI reset signal on a PCI card) (may be
connected to RESET_IN_N and/or POR_IN_N) is active.
Rev. 4.0 — 03 December 2007
Figure 2 on page 1-53
for load conditions.
Min
0.2
- 0.6
1.5
Min
30
11
11
2
2
2
7
12
Figure
Figure
PNX15xx/952x Series
Chapter 1: Integrated Circuit Data
10.
10.
Max
1.8
Max
11
12
28
40
Figure
Units
ns
ns
ns
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11.
© NXP B.V. 2007. All rights reserved.
Figure
Notes
2, 5
4, 5
4, 5
Notes
1
1
1
1,2,3
1,2,3
1
1,7
3,4
3,4
4
5,6
8.
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