PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 305

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

NXP Semiconductors
Volume 1 of 1
Table 18: GPIO Module Status Register for all 12 Timestamp Units
PNX15XX_PNX952X_SER_N_4
Product data sheet
5
4
3
2
1
0
Offset 0x10,4FE4
31:24
23
22
21
20
19
18
17
16
15
14
13
Bit
Symbol
DATA_VALID_5
DATA_VALID_4
DATA_VALID_3
DATA_VALID_2
DATA_VALID_1
DATA_VALID_0
Unused
INT_OE_11_EN
INT_OE_10_EN
INT_OE_9_EN
INT_OE_8_EN
INT_OE_7_EN
INT_OE_6_EN
INT_OE_5_EN
INT_OE_4_EN
INT_OE_3_EN
INT_OE_2_EN
INT_OE_1_EN
INT_ENABLE4
Acces
s
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Value
0
0
0
0
0
0
-
0
0
0
0
0
0
0
0
0
0
0
Rev. 4.0 — 03 December 2007
Description
Data in TSU 5 is ready to be read.
Data in TSU 4 is ready to be read.
Data in TSU 3 is ready to be read.
Data in TSU 2 is ready to be read.
Data in TSU 1 is ready to be read.
Data in TSU 0 is ready to be read.
Internal overrun interrupt enable register for TSU 11
Internal overrun interrupt enable register for TSU 10
Internal overrun interrupt enable register for TSU 9
Internal overrun interrupt enable register for TSU 8
Internal overrun interrupt enable register for TSU 7
Internal overrun interrupt enable register for TSU 6
Internal overrun interrupt enable register for TSU 5
Internal overrun interrupt enable register for TSU 4
Internal overrun interrupt enable register for TSU 3
Internal overrun interrupt enable register for TSU 2
Internal overrun interrupt enable register for TSU 1
0 - Interrupt disabled
1 - Interrupt enabled
0 - Interrupt disabled
1 - Interrupt enabled
0 - Interrupt disabled
1 - Interrupt enabled
0 - Interrupt disabled
1 - Interrupt enabled
0 - Interrupt disabled
1 - Interrupt enabled
0 - Interrupt disabled
1 - Interrupt enabled
0 - Interrupt disabled
1 - Interrupt enabled
0 - Interrupt disabled
1 - Interrupt enabled
0 - Interrupt disabled
1 - Interrupt enabled
0 - Interrupt disabled
1 - Interrupt enabled
0 - Interrupt disabled
1 - Interrupt enabled
Chapter 8: General Purpose Input Output Pins
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
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