EP1S20F780C7 Altera, EP1S20F780C7 Datasheet - Page 31
![IC STRATIX FPGA 20K LE 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP1S20F780C7
Manufacturer Part Number
EP1S20F780C7
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S20F780C7
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1116
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780C7
Manufacturer:
ALTERA
Quantity:
1 238
Company:
Part Number:
EP1S20F780C7
Manufacturer:
ALTERA
Quantity:
453
Company:
Part Number:
EP1S20F780C7L
Manufacturer:
NXP
Quantity:
1 448
Company:
Part Number:
EP1S20F780C7N
Manufacturer:
ALTERA
Quantity:
3 000
Altera Corporation
July 2005
Figure 2–10. LUT Chain & Register Chain Interconnects
The C4 interconnects span four LABs, M512, or M4K blocks up or down
from a source LAB. Every LAB has its own set of C4 interconnects to drive
either up or down.
from an LAB in a column. The C4 interconnects can drive and be driven
by all types of architecture blocks, including DSP blocks, TriMatrix
memory blocks, and vertical IOEs. For LAB interconnection, a primary
LAB or its LAB neighbor can drive a given C4 interconnect.
C4 interconnects can drive each other to extend their range as well as
drive row interconnects for column-to-column connections.
Interconnect
Adjacent LE
Routing to
LUT Chain
Local
Figure 2–11
Local Interconnect
Routing Among LEs
in the LAB
shows the C4 interconnect connections
LE 10
LE 1
LE 2
LE 3
LE 4
LE 5
LE 6
LE 7
LE 8
LE 9
Stratix Device Handbook, Volume 1
Register Chain
Routing to Adjacent
LE's Register Input
Stratix Architecture
2–17