EP1S20F780C7 Altera, EP1S20F780C7 Datasheet - Page 236
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EP1S20F780C7
Manufacturer Part Number
EP1S20F780C7
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet
1.EP1S10F780C7.pdf
(276 pages)
Specifications of EP1S20F780C7
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
420.17MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-1116
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780C7
Manufacturer:
ALTERA
Quantity:
1 238
Company:
Part Number:
EP1S20F780C7
Manufacturer:
ALTERA
Quantity:
453
Company:
Part Number:
EP1S20F780C7L
Manufacturer:
NXP
Quantity:
1 448
Company:
Part Number:
EP1S20F780C7N
Manufacturer:
ALTERA
Quantity:
3 000
Timing Model
4–66
Stratix Device Handbook, Volume 1
LVCMOS
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
1.5-V LVTTL
GTL
GTL+
3.3-V PCI
3.3-V PCI-X 1.0
Compact PCI
AGP 1×
AGP 2×
CTT
SSTL-3 Class I
SSTL-3 Class II
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.5-V HSTL Class I
1.5-V HSTL Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
Table 4–103. Stratix I/O Standard Column Pin Input Delay Adders
Parameter
-5 Speed Grade
Min
External I/O Delay Parameters
External I/O delay timing parameters for I/O standard input and output
adders and programmable input and output delays are specified by
speed grade independent of device density. All of the timing parameters
in this section apply to both flip-chip and wire-bond packages.
Tables 4–103
column and row I/O pins. If an I/O standard is selected other than 3.3-V
LVTTL or LVCMOS, add the selected delay to the external t
t
INSUPLL
–162
–162
–202
–202
Max
221
352
–75
120
–76
–76
–52
–52
–45
19
78
78
I/O parameters shown in
0
0
0
0
0
0
0
and
-6 Speed Grade
Min
4–104
show the input adder delays associated with
–171
–171
–213
–213
Max
232
369
–48
–79
126
–80
–80
–55
–55
19
81
81
0
0
0
0
0
0
0
-7 Speed Grade
Min
Tables 4–54
–196
–196
–244
–244
Max
266
425
–55
–91
144
–92
–92
–63
–63
22
94
94
0
0
0
0
0
0
0
through 4–96.
-8 Speed Grade
Min
Altera Corporation
INSU
–107
–231
–231
–287
–287
–108
–108
Max
January 2006
313
500
–64
170
110
110
–74
–74
26
0
0
0
0
0
0
0
and
Unit
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps