XC4005L-5PQ100C Xilinx Inc, XC4005L-5PQ100C Datasheet - Page 91

• Manufacturer Part Number: XC4005L-5PQ100C
• Description: IC 3.3V FPGA 196 CLB'S 100-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4005L-5PQ100C

• Number Of Logic Elements/cells: 466
• Number Of Labs/clbs: 196
• Total Ram Bits: 6272
• Number Of I /o: 77
• Number Of Gates: 5000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 100-BQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1121

XC4000E IOB Output Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are not measured directly. They are derived from benchmark timing patterns
that are taken at device introduction, prior to any process improvements. For more detailed, more precise, and more up-to-
date information, use the values provided by the XACT timing calculator and used in the simulator. These values can be
printed in tabular format by running LCA2XNF -S.
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC4000E devices unless otherwise noted.
Note 1:
Note 2:
Note 3:
September 18, 1996 (Version 1.04)
Setup and Hold
Output (O) to clock (OK)
Output (O) to clock (OK)
Clock Enable (EC) to
Clock Enable (EC) to
Clock
Clock High
Clock Low
Global Set/Reset (Note 3)
Delay from GSR net to Pad
GSR width
GSR inactive to first active
setup time
hold time
clock (OK) setup
clock (OK) hold
clock (OK) edge
Description
Output timing is measured at pin threshold, with 50pF external capacitive loads (incl. test fixture). Slew-rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on ground
bounce, see the “Additional XC4000 Data” section of the Programmable Logic Data Book.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal
pull-up (default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
Timing is based on the XC4005E. For other devices see the XACT timing calculator.
Speed Grade
Symbol
T
T
T
T
T
T
T
ECOK
OKEC
T
T
MRW
MRO
OOK
OKO
RPO
CH
CL
13.0
Min
5.0
4.8
1.2
4.5
4.5
0
-4
Max
15.0
11.5
Min
4.6
3.5
1.2
4.0
4.0
0
-3
Max
11.8
11.5
Min
3.8
2.7
0.5
4.0
4.0
Preliminary
0
-2
Max
8.7
4-95