XC4005L-5PQ100C Xilinx Inc, XC4005L-5PQ100C Datasheet - Page 59

• Manufacturer Part Number: XC4005L-5PQ100C
• Description: IC 3.3V FPGA 196 CLB'S 100-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4005L-5PQ100C

• Number Of Logic Elements/cells: 466
• Number Of Labs/clbs: 196
• Total Ram Bits: 6272
• Number Of I /o: 77
• Number Of Gates: 5000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 100-BQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1121

Note that DONE is an open-drain output and does not go
High unless an internal pull-up is activated or an external
pull-up is attached. The internal pull-up is activated as the
default by MakeBits, the bitstream generation software.
Release of User I/O After DONE Goes High
By default, the user I/O are released one CCLK cycle after
the DONE pin goes High. If CCLK is not clocked after
DONE goes High, the outputs remain in their initial state —
3-stated, with a 50 k
DONE High to active user I/O is controlled by a MakeBits
option.
September 18, 1996 (Version 1.04)
Figure 50: Start-up Logic
CLEAR MEMORY
LENGTH COUNT
STARTUP
STARTUP.CLK
USER NET
CCLK
FULL
Q3
Q2
*
*
*
S
K
- 100 k
Q
Q0
0
1
M
*
1
0
*
1
0
0
1
CONFIGURATION BIT OPTIONS SELECTED BY USER IN "MAKEBITS"
Q1/Q4
DONE
IN
pull-up. The delay from
D
K
GSR ENABLE
GSR INVERT
STARTUP.GSR
STARTUP.GTS
GTS INVERT
GTS ENABLE
Q
Q1
D
K
CONTROLLED BY STARTUP SYMBOL
IN THE USER SCHEMATIC (SEE
LIBRARIES GUIDE)
Q
Q2
1
0
M
*
Release of Global Set/Reset After DONE Goes
High
By default, Global Set/Reset (GSR) is released two CCLK
cycles after the DONE pin goes High. If CCLK is not
clocked twice after DONE goes High, all flip-flops are held
in their initial set or reset state. The delay from DONE High
to GSR inactive is controlled by a MakeBits option.
Configuration Complete After DONE Goes High
Three full CCLK cycles are required after the DONE pin
goes High, as shown in
not clocked three times after DONE goes High, readback
cannot be initiated and most boundary scan instructions
cannot be used.
D
Q
K
S
R
Q
Q3
GLOBAL SET/RESET OF
ALL CLB AND IOB FLIP-FLOP
IOBs OPERATIONAL PER CONFIGURATION
GLOBAL 3-STATE OF ALL IOBs
D
K
Q
Q4
Figure 49 on page
1
0
X1528
" FINISHED "
ENABLES BOUNDARY
SCAN, READBACK AND
CONTROLS THE OSCILLATOR
61. If CCLK is
DONE
4-63