EP1C20F400C6N Altera, EP1C20F400C6N Datasheet - Page 59

• Manufacturer Part Number: EP1C20F400C6N
• Description: IC CYCLONE FPGA 20K LE 400-FBGA
• Manufacturer: Altera
• Series: Cyclone®r

Specifications of EP1C20F400C6N

• Number Of Logic Elements/cells: 20060
• Number Of Labs/clbs: 2006
• Total Ram Bits: 294912
• Number Of I /o: 301
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 400-FBGA
• Family Name: Cyclone®
• Number Of Logic Blocks/elements: 20060
• # I/os (max): 301
• Frequency (max): 405.2MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 20060
• Ram Bits: 294912
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 400
• Package Type: FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-1687

Figure 2–35. Cyclone I/O Banks
Notes to
(1)
(2)
Altera Corporation
May 2008
Also Supports
Figure 2–35
Figure 2–35
the 3.3-V PCI
I/O Standard
I/O Bank 1
Figure
I/O Bank 1
2–35:
is a top view of the silicon die.
is a graphic representation only. Refer to the pin list and the Quartus II software for exact pin locations.
and DM pins to support a DDR SDRAM or FCRAM interface. I/O bank 1
can also support a DDR SDRAM or FCRAM interface, however, the
configuration input pins in I/O bank 1 must operate at 2.5 V. I/O bank 3
can also support a DDR SDRAM or FCRAM interface, however, all the
JTAG pins in I/O bank 3 must operate at 2.5 V.
Each I/O bank has its own VCCIO pins. A single device can support 1.5-V,
1.8-V, 2.5-V, and 3.3-V interfaces; each individual bank can support a
different standard with different I/O voltages. Each bank also has
dual-purpose VREF pins to support any one of the voltage-referenced
standards (e.g., SSTL-3) independently. If an I/O bank does not use
voltage-referenced standards, the V
Notes
(1),
All I/O Banks Support
■
■
■
■
■
■
■
■
(2)
3.3-V LVTTL/LVCMOS
2.5-V LVTTL/LVCMOS
1.8-V LVTTL/LVCMOS
1.5-V LVCMOS
LVDS
RSDS
SSTL-2 Class I and II
SSTL-3 Class I and II
I/O Bank 2
I/O Bank 4
Power Bus
Individual
REF
pins are available as user I/O pins.
I/O Bank 3
I/O Bank 3
Also Supports
the 3.3-V PCI
I/O Standard
I/O Structure
Preliminary
2–53