ST72F324BK6TAS STMicroelectronics, ST72F324BK6TAS Datasheet - Page 54

• Manufacturer Part Number: ST72F324BK6TAS
• Description: 8-BIT MCU
• Manufacturer: STMicroelectronics

Power saving modes
8.4
8.4.1
Note:
Caution:
54/198
Active Halt and Halt modes
Active Halt and Halt modes are the two lowest power consumption modes of the MCU. They
are both entered by executing the ‘HALT’ instruction. The decision to enter either in Active
Halt or Halt mode is given by the MCC/RTC interrupt enable flag (OIE bit in the MCCSR
register).
Table 26.
Active Halt mode
Active Halt mode is the lowest power consumption mode of the MCU with a real-time clock
available. It is entered by executing the ‘HALT’ instruction when the OIE bit of the Main Clock
Controller Status register (MCCSR) is set (see
time clock and beeper (MCC/RTC) on page 69
The MCU can exit Active Halt mode on reception of either an MCC/RTC interrupt, a specific
interrupt (see
means of an interrupt, no 256 or 4096 CPU cycle delay occurs. The CPU resumes operation
by servicing the interrupt or by fetching the reset vector which woke it up (see
When entering Active Halt mode, the I[1:0] bits in the CC register are forced to ‘10b’ to
enable interrupts. Therefore, if an interrupt is pending, the MCU wakes up immediately.
In Active Halt mode, only the main oscillator and its associated counter (MCC/RTC) are
running to keep a wake-up time base. All other peripherals are not clocked except those
which get their clock supply from another clock generator (such as external or auxiliary
oscillator).
The safeguard against staying locked in Active Halt mode is provided by the oscillator
interrupt.
As soon as the interrupt capability of one of the oscillators is selected (MCCSR.OIE bit set),
entering Active Halt mode while the Watchdog is active does not generate a reset.
This means that the device cannot spend more than a defined delay in this power saving
mode.
When exiting Active Halt mode following an interrupt, OIE bit of MCCSR register must not be
cleared before t
on option byte). Otherwise, the ST7 enters Halt mode for the remaining t
Figure 24. Active Halt timing overview
1. This delay occurs only if the MCU exits Active Halt mode by means of a reset.
MCCSR OIE bit
0
1
MCC/RTC low power mode selection
Table 25: Interrupt
DELAY
after the interrupt occurs (t
Halt mode
Active Halt mode
[MCCSR.OIE = 1]
Power saving mode entered when HALT instruction is executed
Run
instruction
Doc ID13466 Rev 4
Halt
mapping) or a reset. When exiting Active Halt mode by
Active
Halt
256 or 4096 CPU
cycle delay
interrupt
Reset
or
Section 10.2: Main clock controller with real-
for more details on the MCCSR register).
DELAY
(1)
vector
= 256 or 4096 t
Fetch
Run
CPU
DELAY
delay depending
ST72324B-Auto
Figure
period.

25).