ST72F324BK6TAS STMicroelectronics, ST72F324BK6TAS Datasheet - Page 156

• Manufacturer Part Number: ST72F324BK6TAS
• Description: 8-BIT MCU
• Manufacturer: STMicroelectronics

Electrical characteristics
Note:
12.6.5
12.7
12.7.1
156/198
To reduce disturbance to the RC oscillator, it is recommended to place decoupling
capacitors between V
PLL characteristics
Table 98.
1. Data characterized but not tested
The user must take the PLL jitter into account in the application (for example in serial
communication or sampling of high frequency signals). The PLL jitter is a periodic effect,
which is integrated over several CPU cycles. Therefore the longer the period of the
application signal, the less it will be impacted by the PLL jitter.
Figure 67
2 MHz. At frequencies of less than 125 kHz, the jitter is negligible.
Figure 67. Integrated PLL jitter vs signal frequency
1. Measurement conditions: f
Memory characteristics
RAM and hardware registers
Table 99.
1. Minimum V
 f
Symbol
Symbol
hardware registers (only in Halt mode). Not tested in production.
V
CPU
f
RM
OSC
/f
CPU
shows the PLL jitter integrated on application signals in the range 125 kHz to
Data retention mode
DD
PLL characteristics
RAM and hardware registers
PLL input frequency range
Instantaneous PLL jitter
supply voltage without losing data stored in RAM (in Halt mode or under reset) or in
Parameter
DD
Parameter
CPU
+/-Jitter (%)
and V
= 8 MHz
1.2
0.8
0.6
0.4
0.2
1
0
(1)
Doc ID13466 Rev 4
SS
4 MHz
as shown in
(1)
2 MHz
Halt mode (or reset)
Application Frequency
f
1 MHz 500 kHz 250 kHz 125 kHz
OSC
Conditions
Figure 85 on page
Conditions
= 4 MHz
(1)
Max
Typ
Min
1.6
Min
2
173.
Typ
Typ
0.7
ST72324B-Auto
Max
Max
4
2
MHz
Unit
Unit
%
V