ST72F324BK6TAS STMicroelectronics, ST72F324BK6TAS Datasheet - Page 43

• Manufacturer Part Number: ST72F324BK6TAS
• Description: 8-BIT MCU
• Manufacturer: STMicroelectronics

ST72324B-Auto
Note:
7.2.2
7.2.3
7.2.4
1
2
When an interrupt request is not serviced immediately, it is latched and then processed
when its software priority combined with the hardware priority becomes the highest one.
The hardware priority is exclusive while the software one is not. This allows the previous
process to succeed with only one interrupt.
Reset and TRAP can be considered as having the highest software priority in the decision
process.
Different interrupt vector sources
Two interrupt source types are managed by the ST7 interrupt controller: the non-maskable
type (reset, TRAP) and the maskable type (external or from internal peripherals).
Non-maskable sources
These sources are processed regardless of the state of the I1 and I0 bits of the CC register
(see
corresponding vector is loaded in the PC register and the I1 and I0 bits of the CC are set to
disable interrupts (level 3). These sources allow the processor to exit Halt mode.
TRAP (non-maskable software interrupt)
This software interrupt is serviced when the TRAP instruction is executed. It will be serviced
according to the flowchart in
Reset
The reset source has the highest priority in the ST7. This means that the first current routine
has the highest software priority (level 3) and the highest hardware priority.
See the reset chapter for more details.
Maskable sources
Maskable interrupt vector sources can be serviced if the corresponding interrupt is enabled
and if its own interrupt software priority (in ISPRx registers) is higher than the one currently
being serviced (I1 and I0 in CC register). If any of these two conditions is false, the interrupt
is latched and thus remains pending.
External interrupts
External interrupts allow the processor to Exit from Halt low power mode. External interrupt
sensitivity is software selectable through the External Interrupt Control register (EICR).
External interrupt triggered on edge will be latched and the interrupt request automatically
cleared upon entering the interrupt service routine.
If several input pins of a group connected to the same interrupt line are selected
simultaneously, these will be logically ORed.
Peripheral interrupts
Usually the peripheral interrupts cause the MCU to Exit from Halt mode except those
mentioned in
is set in the peripheral status registers and if the corresponding enable bit is set in the
Figure
16). After stacking the PC, X, A and CC registers (except for reset), the
Table 25: Interrupt
Figure
Doc ID13466 Rev 4
mapping. A peripheral interrupt occurs when a specific flag
16.
Interrupts
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