MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 35

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

Figure 19: READ/BUSY# Open Drain
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
driver enables multiple R/B# outputs to be OR-tied. Typically, R/B# is connected to an
interrupt pin on the system controller.
The combination of Rp and capacitive loading of the R/B# circuit determines the rise
time of the R/B# signal. The actual value used for Rp depends on the system timing re-
quirements. Large values of Rp cause R/B# to be delayed significantly. Between the 10%
and 90% points on the R/B# waveform, the rise time is approximately two time con-
stants (TC).
Where R = Rp (resistance of pull-up resistor), and C = total capacitive load.
The fall time of the R/B# signal is determined mainly by the output impedance of the
R/B# signal and the total load capacitance. Approximate Rp values using a circuit load
of 100pF are provided in Figure 24 (page 38).
The minimum value for Rp is determined by the output drive capability of the R/B#
signal, the output voltage swing, and V
Where Σ
V
V
CC
SS
IL
is the sum of the input currents of all devices tied to the R/B# pin.
I
Rp =
OL
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
V
Device
CC
(MAX) - V
I
OL
TC = R × C
35
R/B#
Open drain output
+ Σ
OL
IL
Asynchronous Interface Bus Operation
Rp
(MAX)
CC
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