MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 207

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

Figure 141: Bank Read – Without Auto Precharge
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Case 2:
Case 1:
Command
BA0, BA1
Address
DQ
DQ
DQS
DQS
t
t
AC (MAX) and
CK#
CKE
A10
AC (MIN) and
DM
CK
7,8
7,8
7
7
t
t
IS
IS
NOP
T0
t
t
DQSCK (MIN)
DQSCK (MAX)
t
t
1
IH
IH
Notes:
t
Bank x
ACTIVE
IS
t
IS
Row
Row
T1
t
IH
t
IH
t
1. NOP commands are shown for ease of illustration; other commands may be valid at
2. BL = 4 in the case shown.
3. PRE = PRECHARGE.
4. Disable auto precharge.
5. Bank x at T5 is “Don’t Care” if A10 is HIGH at T5.
6. The PRECHARGE command can only be applied at T5 if
7. Refer to Figure 125 (page 189) and Figure 126 (page 190) for DQS and DQ timing details.
8. D
CK
t
t
t
RCD
RAS
RC
these times.
OUT
NOP
6
T2
n = data out from column n.
1
t
CH
t
CL
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
Bank x
READ
t
Note 4
t
Col n
IS
LZ (MIN)
T3
t
2
IH
CL = 2
t
RPRE
t
t
AC (MIN)
LZ (MIN)
NOP
207
T4
t
1
AC (MAX)
D
t
OUT
RPRE
n
t
DQSCK (MIN)
One bank
All banks
Bank x
D
n + 1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
PRE
OUT
T5
D
t
OUT
DQSCK (MAX)
n
3
5
D
n + 2
T5n
OUT
D
n + 1
OUT
D
n + 3
NOP
t
OUT
T6
RPST
D
n + 2
OUT
Don’t Care
1
t
RP
T6n
t
HZ (MAX)
t
D
n + 3
RPST
OUT
t
RAS (MIN) is met.
NOP
T7
© 2009 Micron Technology, Inc. All rights reserved.
1
Transitioning Data
Auto Precharge
ACTIVE
Bank x
Row
Row
T8