MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 199

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

Figure 135: WRITE-to-READ – Interrupting
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Command
Address
t
t
t
DQSS (NOM)
DQSS (MIN)
DQSS (MAX)
DQS
DQS
DQS
DQ
DQ
DQ
CK#
DM
DM
DM
CK
4
5
4
5
4
5
WRITE
Bank a,
Col b
T0
Notes:
t
t
t
1,2
DQSS
DQSS
DQSS
1. An interrupted burst of 4 is shown; 2 data elements are written.
2. A10 is LOW with the WRITE command (auto precharge is disabled).
3.
4. DQS is required at T2 and T2n (nominal case) to register DM.
5. D
D
b
IN
t
NOP
WTR is referenced from the first positive CK edge after the last data-in pair.
D
T1
IN
b
IN
b = data-in for column b; D
b+1
D
D
b
IN
IN
T1n
b+1
D
IN
b+1
D
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
IN
NOP
T2
t
WTR
T2n
3
199
Bank a,
READ
Col n
T3
OUT
n = data-out for column n.
Micron Technology, Inc. reserves the right to change products or specifications without notice.
T4
NOP
Don’t Care
CL = 3
CL = 3
CL = 3
T5
NOP
© 2009 Micron Technology, Inc. All rights reserved.
WRITE Operation
T5n
Transitioning Data
D
D
D
OUT
n
OUT
n
OUT
n
T6
NOP
D
n + 1
D
n + 1
D
n + 1
OUT
OUT
OUT
T6n