MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 31

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

Asynchronous Addresses
Figure 15: Asynchronous Address Latch Cycle
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
WE#
ALE
I/Ox
CLE
CE#
An asynchronous address is written from I/O[7:0] to the address register on the rising
edge of WE# when CE# is LOW, ALE is HIGH, CLE is LOW, and RE# is HIGH.
Bits that are not part of the address space must be LOW (see Device and Array Organiza-
tion). The number of cycles required for each command varies. Refer to the command
descriptions to determine addressing requirements.
Addresses are typically ignored by die (LUNs) that are busy (RDY = 0); however, some
addresses are accepted by die (LUNs) even when they are busy; for example, like ad-
dress cycles that follow the READ STATUS ENHANCED (78h) command.
t CS
t CLS
t WP
t ALS
t DS
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t WC
t DH
t ALH
t WH
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
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Asynchronous Interface Bus Operation
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
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© 2009 Micron Technology, Inc. All rights reserved.
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