MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 144

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

Table 44: I
Notes 1–5 apply to all the parameters/conditions in this table; V
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
Parameter/Condition
Operating 1 bank active precharge current:
=
Address inputs are switching every 2 clock cycles; Data bus in-
puts are stable
Precharge power-down standby current: All banks idle; CKE is
LOW; CS is HIGH;
are switching; Data bus inputs are stable
Precharge power-down standby current: Clock stopped; All
banks idle; CKE is LOW; CS is HIGH, CK = LOW, CK# = HIGH; Ad-
dress and control inputs are switching; Data bus inputs are stable
Precharge nonpower-down standby current: All banks idle; CKE
= HIGH; CS = HIGH;
are switching; Data bus inputs are stable
Precharge nonpower-down standby current: Clock stopped; All
banks idle; CKE = HIGH; CS = HIGH; CK = LOW, CK# = HIGH; Ad-
dress and control inputs are switching; Data bus inputs are stable
Active power-down standby current: 1 bank active; CKE = LOW;
CS = HIGH;
switching; Data bus inputs are stable
Active power-down standby current: Clock stopped; 1 bank ac-
tive; CKE = LOW; CS = HIGH; CK = LOW; CK# = HIGH; Address
and control inputs are switching; Data bus inputs are stable
Active nonpower-down standby: 1 bank active; CKE = HIGH; CS
= HIGH;
ing; Data bus inputs are stable
Active nonpower-down standby: Clock stopped; 1 bank active;
CKE = HIGH; CS = HIGH; CK = LOW; CK# = HIGH; Address and
control inputs are switching; Data bus inputs are stable
Operating burst read: 1 bank active; BL = 4; CL = 3;
(MIN); Continuous READ bursts; Iout = 0mA; Address inputs are
switching every 2 clock cycles; 50% data changing each burst
Operating burst write: One bank active; BL = 4;
(MIN); Continuous WRITE bursts; Address inputs are switching;
50% data changing each burst
Auto refresh: Burst refresh; CKE = HIGH; Ad-
dress and control inputs are switching; Data
bus inputs are stable
Deep power-down current: Address and control pins are stable;
Data bus inputs are stable
t
CK (MIN); CKE is HIGH; CS is HIGH between valid commands;
t
CK =
t
DD
CK =
t
CK (MIN); Address and control inputs are switch-
Specifications and Conditions, –40°C to +105°C (x32)
t
t
CK (MIN); Address and control inputs are
CK =
t
CK =
t
CK (MIN); Address and control inputs
t
CK (MIN); Address and control inputs
t
RC =
168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
t
t
t
CK =
RFC = 138ns
RFC =
t
RC (MIN);
t
CK =
t
CK
t
REFI
t
CK
144
t
CK
Electrical Specifications – I
DD
Symbol
/V
I
I
I
I
I
I
I
I
I
I
DD2NS
I
DD3NS
DD2PS
DD3PS
DD4W
DDQ
I
DD2N
DD3N
DD4R
I
DD5A
I
DD2P
DD3P
DD0
DD5
DD8
Micron Technology, Inc. reserves the right to change products or specifications without notice.
= 1.70–1.95V
1500
1500
100
150
150
170
19
13
21
18
13
15
-5
9
9
1500
1500
100
145
145
170
-54
19
13
21
18
13
15
9
9
Max
1500
1500
140
140
170
80
19
12
20
17
13
15
-6
© 2009 Micron Technology, Inc. All rights reserved.
9
9
DD
1500
1500
120
120
170
-75
70
16
12
19
15
13
15
9
9
Parameters
Unit Notes
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
μA
μA
μA
10, 11
7, 13
7, 8
10
6
7
9
9
8
6
6
6
6