MT29C4G48MAZAPAKD-5 IT Micron Technology Inc, MT29C4G48MAZAPAKD-5 IT Datasheet - Page 32

• Manufacturer Part Number: MT29C4G48MAZAPAKD-5 IT
• Description: MICMT29C4G48MAZAPAKD-5_IT 4G+2G MCP
• Manufacturer: Micron Technology Inc

Asynchronous Data Input
Figure 16: Asynchronous Data Input Cycles
PDF: 09005aef83ba4387
168ball_nand_lpddr_j42p_j4z2_j4z3_omap.pdf – Rev. H 3/11
WE#
I/Ox
CE#
ALE
CLE
Data is written from I/O[7:0] to the cache register of the selected die (LUN) on the rising
edge of WE# when CE# is LOW, ALE is LOW, CLE is LOW, and RE# is HIGH.
Data input is ignored by die (LUNs) that are not selected or are busy (RDY = 0). Data is
written to the data register on the rising edge of WE# when CE#, CLE, and ALE are LOW,
and the device is not busy.
Data is input on I/O[7:0] on x8 devices and on I/O[15:0] on x16 devices.
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168-Ball NAND Flash and LPDDR PoP (TI OMAP) MCP
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Asynchronous Interface Bus Operation
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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© 2009 Micron Technology, Inc. All rights reserved.
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