72T7285L4-4BB IDT, Integrated Device Technology Inc, 72T7285L4-4BB Datasheet - Page 51
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72T7285L4-4BB
Manufacturer Part Number
72T7285L4-4BB
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.72T7285L4-4BB.pdf
(53 pages)
Specifications of 72T7285L4-4BB
Configuration
Dual
Density
1.125Mb
Access Time (max)
3.4ns
Word Size
72b
Organization
16Kx72
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
BGA
Clock Freq (max)
225MHz
Operating Supply Voltage (typ)
2.5V
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Supply Current
130mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
324
Lead Free Status / Rohs Status
Not Compliant
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
signals of multiple devices. Status flags can be detected from any one device.
The exceptions are the EF and FF functions in IDT Standard mode and the IR
and OR functions in FWFT mode. Because of variations in skew between RCLK
and WCLK, it is possible for EF/FF deassertion and IR/OR assertion to vary
by one cycle between FIFOs. In IDT Standard mode, such problems can be
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
Word width may be increased simply by connecting together the control
GATE
(1)
FIRST WORD FALL THROUGH/
DATA IN
SERIAL INPUT (FWFT/SI)
SERIAL CLOCK (SCLK)
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FULL FLAG/INPUT READY (FF/IR)
Figure 36. Block Diagram of 16,384 x 144, 32,768 x 144, 65,536 x 144 and 131,072 x 144 Width Expansion
FULL FLAG/INPUT READY (FF/IR) #2
RETRANSMIT (RT)
m + n
PROGRAMMABLE (PAF)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
HALF-FULL FLAG (HF)
D
0
- D
LOAD (LD)
m
m
#1
72T72105
72T72115
72T7285
72T7295
FIFO
IDT
#1
D
m+1
m
- D
Q
51
n
0
n
- Qm
avoided by creating composite flags, that is, ANDing EF of every FIFO, and
separately ANDing FF of every FIFO. In FWFT mode, composite flags can
be created by ORing OR of every FIFO, and separately ORing IR of every
FIFO.
72T7295/72T72105/72T72115 devices. D
144-bit wide input bus and Q
bus. Any word width can be attained by adding additional IDT72T7285/
72T7295/72T72105/72T72115 devices.
Figure 36 demonstrates a width expansion using two IDT72T7285/
72T72105
72T72115
72T7285
72T7295
FIFO
IDT
#2
READ CLOCK (RCLK)
READ CHIP SELECT (RCS)
n
READ ENABLE (REN)
OUTPUT ENABLE (OE)
EMPTY FLAG/OUTPUT READY (EF/OR) #2
EMPTY FLAG/OUTPUT READY (EF/OR) #1
PROGRAMMABLE (PAE)
Q
m+1
- Q
0
-Q
n
71
from each device form a 144-bit wide output
COMMERCIAL AND INDUSTRIAL
m + n
0
- D
TEMPERATURE RANGES
71
DATA OUT
from each device form a
5994 drw41
GATE
(1)