72T7285L4-4BB IDT, Integrated Device Technology Inc, 72T7285L4-4BB Datasheet - Page 20
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72T7285L4-4BB
Manufacturer Part Number
72T7285L4-4BB
Description
Manufacturer
IDT, Integrated Device Technology Inc
Datasheet
1.72T7285L4-4BB.pdf
(53 pages)
Specifications of 72T7285L4-4BB
Configuration
Dual
Density
1.125Mb
Access Time (max)
3.4ns
Word Size
72b
Organization
16Kx72
Sync/async
Synchronous
Expandable
Yes
Bus Direction
Uni-Directional
Package Type
BGA
Clock Freq (max)
225MHz
Operating Supply Voltage (typ)
2.5V
Operating Supply Voltage (min)
2.375V
Operating Supply Voltage (max)
2.625V
Supply Current
130mA
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
324
Lead Free Status / Rohs Status
Not Compliant
MARK is HIGH), a retransmit can be initiated by a rising RCLK edge while the
retransmit input (RT) is LOW. REN must be HIGH (reads disabled) before
bringing RT LOW. The device indicates the start of retransmit setup by setting
OR HIGH.
RCLK edge after retransmit setup is complete, (RT goes HIGH), the contents
of the first retransmit location are loaded onto the output register. Since FWFT
mode is selected, the first word appears on the outputs regardless of REN, a
LOW on REN is not required for the first word. Reading all subsequent words
requires a LOW on REN to enable the rising RCLK edge. See Figure 19,
Retransmit from Mark timing (FWFT mode), for the relevant timing diagram.
TABLE 5 — I/O CONFIGURATION
IDT72T7285/72T7295/72T72105/72T72115 2.5V TeraSync™ ™ ™ ™ ™ 72-BIT FIFO
16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72
Once a marked location has been set (and the device is still in retransmit mode,
When OR goes LOW, retransmit setup is complete and on the next rising
Note, there must be a minimum of 32 bytes of data between the write pointer
WHSTL: HIGH = HSTL
Dn (I/P)
WCLK/WR (I/P)
WEN (I/P)
WCS (I/P)
WHSTL SELECT
LOW = LVTTL
RCLK/RD (I/P)
RCS (I/P)
MARK (I/P)
REN (I/P)
OE (I/P)
RT (I/P)
Qn (O/P)
RHSTL: HIGH = HSTL
RHSTL SELECT
LOW = LVTTL
EF/OR (O/P)
PAF (O/P)
EREN (O/P)
PAE (O/P)
FF/IR (O/P)
HF (O/P)
ERCLK (O/P)
TDO (O/P)
20
SCLK (I/P)
LD (I/P)
MRS (I/P)
TCK (I/P)
TMS (I/P)
SEN (I/P)
FWFT/SI (I/P)
and read pointer when the MARK is asserted. (32 bytes = 16 word = 8 long
words). Also, once the MARK is set, the write pointer will not increment past the
“marked” location until the MARK is deasserted. This prevents “overwriting” of
retransmit data.
HSTL/LVTTL I/O
I/O, via two select pins, WHSTL and RHSTL respectively. All other control pins
are selectable via SHSTL, see Table 5 for details of groupings.
the power consumption (in stand-by mode by utilizing the WCS input).
and are purely device configuration pins.
SHSTL: HIGH = HSTL
Both the write port and read port are user selectable between HSTL or LVTTL
Note, that when the write port is selected for HSTL mode, the user can reduce
All “Static Pins” must be tied to V
SHSTL SELECT
LOW = LVTTL
PRS (I/P)
TRST (I/P)
TDI (I/P)
CC
COMMERCIAL AND INDUSTRIAL
or GND. These pins are LVTTL only,
IW (I/P)
BM (I/P)
ASYR (I/P)
IP (I/P)
FSEL1 (I/P)
SHSTL (I/P)
RHSTL (I/P)
TEMPERATURE RANGES
STATIC PINS
LVTTL ONLY
OW (I/P)
ASYW (I/P)
BE (I/P)
FSEL0 (I/P)
PFM (I/P)
WHSTL (I/P)