82V1068PF8 IDT, Integrated Device Technology Inc, 82V1068PF8 Datasheet - Page 39

• Manufacturer Part Number: 82V1068PF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V1068PF8

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3.135V
• Single Supply Voltage (max): 3.6V
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

IDT82V1068 OCTAL PROGRAMMABLE PCM CODEC
3.4.2
LC1:
LC2:
LOCAL COMMANDS LIST
Coefficient Selection, Read/Write (00H/80H)
The Coefficient Selection bits (CS[7:0]) are used to control the digital filters and function blocks on the corresponding channel such as
the Impedance Matching Filter, Echo Cancellation Filter, High-Pass Filter, Gain for Impedance Scaling, Gain in Transmit/Receive Path
and Frequency Response Correction in Transmit/Receive Path. See
It should be noted that the Impedance Matching Filter and the Gain for Impedance Scaling are working together to adjust the impedance.
That is to say, The CS[0] and CS[2] bits should be set to the same value to ensure the correct operation.
CS[0] = 0:
CS[0] = 1:
CS[1] = 0:
CS[1] = 1:
CS[2] = 0:
CS[2] = 1:
CS[3] = 0:
CS[3] = 1:
CS[4] = 0:
CS[4] = 1:
CS[5] = 0:
CS[5] = 1:
CS[6] = 0:
CS[6] = 1:
CS[7] = 0:
CS[7] = 1:
Refer to
Loopback Control, PCM Receive Path Cutoff and SLIC Input Interrupt Enable, Read/Write (01H/81H)
The loopback control bits (DLB_1BIT, ALB_1BIT and DLB_PCM) determine the loopback status on the corresponding channel. See
Figure 9 on page 19
DLB_1BIT = 0: The digital loopback via Onebit on the corresponding channel is disabled (default);
DLB_1BIT = 1: The digital loopback via Onebit on the corresponding channel is enabled;
ALB_1BIT = 0: The analog loopback via Onebit on the corresponding channel is disabled (default);
ALB_1BIT = 1: The analog loopback via Onebit on the corresponding channel is enabled;
DLB_PCM = 0: The digital loopback via the PCM interface on the corresponding channel is disabled (default);
DLB_PCM = 1: The digital loopback via the PCM interface on the corresponding channel is enabled. In this loopback mode, the digital
Command
Command
I/O Data
I/O Data
Figure 18 on page 53
The Impedance Matching Filter is disabled (default);
The Impedance Matching Filter coefficient is set by IMF RAM;
The Echo Cancellation Filter is disabled (default);
The Echo Cancellation Filter coefficient is set by ECF RAM;
The Gain for Impedance Scaling is disabled (default);
The Gain for Impedance Scaling coefficient is set by GIS RAM;
The High-Pass Filter is bypassed/disabled;
The High-Pass Filter is enabled (default);
The Frequency Response Correction in Transmit Path is bypassed (default);
The Frequency Response Correction in Transmit Path coefficient is set by FRX RAM;
The Gain in Transmit Path is 0 dB (default);
The Gain in Transmit Path coefficient is set by GTX RAM;
The Frequency Response Correction in Receive Path is bypassed (default);
The Frequency Response Correction in Receive Path coefficient is set by FRR RAM;
The Gain in Receive Path is 0 dB (default);
The Gain in Receive Path coefficient is set by GRX RAM.
data received from the DR1/2 pin will be switched by the time slot setting and then transmitted out from the DX1/2 pin.
CS[7]
R/W
R/W
IE[3]
b7
b7
for details.
for the Coe-RAM address mapping.
CS[6]
IE[2]
b6
b6
0
0
CS[5]
IE[1]
b5
b5
0
0
CS[4]
IE[0]
39
b4
b4
0
0
Figure 9 on page 19
CUTOFF
CS[3]
b3
b3
0
0
DLB_PCM
CS[2]
b2
b2
0
0
for details.
INDUSTRIAL TEMPERATURE RANGE
ALB_1BIT
CS[1]
b1
b1
0
0
DLB_1BIT
CS[0]
b0
b0
0
1