82V1068PF8 IDT, Integrated Device Technology Inc, 82V1068PF8 Datasheet - Page 24

• Manufacturer Part Number: 82V1068PF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V1068PF8

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3.135V
• Single Supply Voltage (max): 3.6V
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

IDT82V1068 OCTAL PROGRAMMABLE PCM CODEC
2.10
The level meter is designed to emulate the off-chip PCM test equipment
to facilitate the line-card, subscriber line and user telephone set
monitoring. The level meter tests the returned signal and reports the
measurement result via the MPI/GCI interface. When combined with the
dual tone generators and the loopbacks, this allows the microprocessor
to test channel integrity. The CS[2:0] bits in Global Command 19 select
the channel on which the signal will be metered.
Global Command 19. A Level Meter Counter register is provided for this
function. It can be accessed by Global Command 18. This register is
used to configure the number of time cycles for the sampling PCM data
(8 kHz sampling rate). The output of the level metering will be sent to the
Level Meter Result Low and Level Meter Result High registers (Global
Command 16 and 17). The LMRL register contains the lower 7 bits of
the output and a data-ready bit (DRLV), the LMRH register contains the
higher 8 bits of the output. An internal accumulator sums the rectified
samples until the number configured by Level Meter Counter register is
reached. By then, the DRLV bit is set to 1 and accumulation result is
latched into the LMRL and LMRH registers simultaneously.
DRLV bit will be set to high again when a new data is available. The
contents in LMRL and LMRH will be overwritten by later metering result
if they are not read out yet. To read the Level Metering result register, it
is highly recommended to read LMRL first.
meter operation. When the L/C bit is 1, the level meter will measure the
linear PCM data. If the DRLV bit is 1, the measure result will be output to
The IDT82V1068 has a level meter shared by all 8 signal channels.
The level metering function is enabled by setting the LMO bit to 1 in
Once the LMRH register is read, the DRLV bit will be reset. The
The L/C bit in Global Command 19 determines the mode of level
LEVEL METERING
24
LMRL and LMRH. When the L/C bit is 0, the compressed PCM will be
output transparently to LMRH.
Application Note.
2.11
independently by Local Command 10. When the channel is powered
down (enters standby mode), the PCM data transmission and reception
together with the D-to-A and A-to-D conversions are disabled. In this
way, the power consumption of the device can be reduced. When the
IDT82V1068 is powered up or reset, all eight channels will be powered
down. All circuits that contain programmed information retain their data
when powered down. In MPI mode, the microprocessor interface is
always active so that new command could be received and executed. In
GCI mode, the monitor channel of any time slot is always on so that new
command could be accepted at any time.
2.12
mode, the PLL block is turned off and the DSP operation is disabled.
This mode saves much more power consumption than the standby
mode. In this mode, only Global Commands and Local Commands can
be executed. The RAM operation is disabled as the internal clock has
been turned off. The PLL block is powered down by Global Command
26. The suspend mode can be entered by powering down the PLL
blocks and all channels.
The calculation and method of level metering will be described in
Each individual channel of the IDT82V1068 can be powered down
A suspend mode is offered to the whole chip to save power. In this
CHANNEL POWER DOWN/STANDBY MODE
POWER DOWN PLL/SUSPEND MODE
INDUSTRIAL TEMPERATURE RANGE