82V1068PF8 IDT, Integrated Device Technology Inc, 82V1068PF8 Datasheet - Page 26

• Manufacturer Part Number: 82V1068PF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V1068PF8

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3.135V
• Single Supply Voltage (max): 3.6V
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

IDT82V1068 OCTAL PROGRAMMABLE PCM CODEC
3.1.6
Command (Global Command 6) must be used first to specify which
channel will be addressed, then the Local Commands follows. If Global
Command 6 enables more than one channel, all the channels enabled
will be addressed by one Local Command at one time.
pin) and the b4 bit in Program Start Byte would indicate which channel to
be addressed.
Local Registers of the selected channel(s) will be addressed.
method for reading/writing the Local Registers. According to the value of
the b[1:0] bits specified in a Local Command, there will be 1 to 4
adjacent local registers that will be read/written automatically with the
highest order first. For example, if the b[1:0] bits specified in the Local
Command is ‘11’, 4 adjacent registers will be addressed by this
Command. If b[1:0] = ‘10’, 3 adjacent registers will be addressed. Refer
to
Table 4 Consecutive Adjacent Addressing
the first byte on the CI pin as a command byte, and the rest byte(s) as
data byte(s). To write another command, the CS pin must be changed
from low to high to finish the previous command and then changed from
high to low to indicate the start of the next command. When a read/write
operation is completed, the CS pin must be pulled to high in 8-bit time.
can be stopped by the CS signal at any time. When the CS pin is
changed from low to high, the operation on the current register and the
next adjacent registers will be aborted. But the results of the previous
operation are still remained.
can not be stopped once a command is initiated. For write command,
the number of bytes following the command must be as same as the
number of registers being written.
3.1.7
Table 4
b4
In MPI mode, when using Local Commands, the Channel Enable
In GCI mode, both the location of the time slot (determined by the TS
The b[4:0] bits in a Local Command determine which one of the
The IDT82V1068 provides a consecutive adjacent addressing
X
X
X
X
In MPI mode, when the CS pin becomes low, the IDT82V1068 treats
In MPI mode, the procedure of the consecutive adjacent addressing
In GCI mode, the procedure of the consecutive adjacent addressing
The address of the 27 Global Registers is as the following:
00000 - 11001 (Global Register 1- 26)
11100 (Global Register 27)
Address Specified in Local
(b1b0 = 10, 3 bytes of data)
(b1b0 = 01, 2 bytes of data)
(b1b0 = 11, 4 bytes of data)
(b1b0 = 00, 1 byte of data)
b3
X
X
X
X
for details.
Commands
ADDRESSING LOCAL REGISTER
ADDRESSING THE GLOBAL REGISTERS
b2
X
X
X
X
b1
1
1
0
0
b0
1
0
1
0
In/Out Data
Byte 1
Byte 2
Byte 3
Byte 4
Byte 1
Byte 2
Byte 3
Byte 1
Byte 2
Byte 1
Registers to Be
Addressed
XXX11
XXX10
XXX01
XXX00
XXX10
XXX01
XXX00
XXX01
XXX00
XXX00
26
and not 11010, because the address space from 11010 to 11011 are
reserved.
a consecutive adjacent addressing for read/write operation, as it does
for the Local Registers. In MPI mode, the procedure of the consecutive
adjacent addressing for Global Registers can also be stopped by the CS
signal at any time. But in GCI mode, the procedure can not be stopped
once a command is initiated. For the 27th Global Register (address is
11100), once a read/write procedure is completed, the CS pin must be
pulled to high. It should be noted that, in GCI mode, the Global
Command for all 8 channels can be transferred via any GCI time slot.
3.1.8
They are divided into 5 blocks, each block contains 8 words. The 5
blocks are:
Filter coefficient;
Filter coefficient;
Scaling;
containing the coefficients for the Frequency Response Correction in
Transmit Path and Gain in Transmit Path;
containing the coefficients for the Frequency Response Correction in
Receive Path and Gain in Receive Path.
RAM word, 16 bits (b[15:0]) (or, two 8-bit bytes) are needed to fulfill with
MSB first, but the lowest two bits (b[1:0]) will be ignored. When being
read, each Coe-RAM word will output 16 bits with MSB first, but the last
two bits (b[1:0]) are meaningless.
(Channel Enable) must be used first to specify the channel(s), then the
address (b[4:0]) in the following RAM Command will indicate which block
of the Coe-RAM of the specified the channel(s) will be addressed.
pin) and the b4 bit in the Program Start Byte will indicate which channel
will be addressed.
RAM. That is, when executing a Coe-RAM Command, all 8 words in the
specified block will be addressed automatically, with the highest order
word first.
procedure can be stopped by the CS signal at any time. When the CS
signal is changed from low to high, the operation on the current word
and the next adjacent words will be aborted. But the results of the
previous operation are still remained.
3.1.9
channels. Four FSK-RAMs are provided for the four FSK generators
respectively. Before accessing the FSK-RAM, the Global Command 25
must be used first to specify one or more FSK generator(s), then the
It should be noted that the address of Global Register 27 is 11100
For the adjacent 26 Global Registers, the IDT82V1068 also provides
The IDT82V1068 provides 40 words of Coe-RAM for each channel.
- IMF RAM (Word 0 - Word 7), containing the Impedance Matching
- ECF RAM (Word 8 - Word 15), containing the Echo Cancellation
- GIS RAM (Word 16 - Word 23), containing the Gain of Impedance
- FRX RAM (Word 24 - Word 30) and GTX RAM (Word 31),
- FRR RAM (Word 32 - Word 38) and GRX RAM (Word 39),
Refer to
Each word in the Coe-RAM is 14-bit (b[13:0]) wide. To write a Coe-
In MPI mode, when addressing the Coe-RAM, Global Command 6
In GCI mode, both the location of time slot (determined by the TS
The address in a Coe-RAM Command locates a block of the Coe-
In MPI mode, when reading/writing a Coe-RAM block, the addressing
The IDT82V1068 provides four FSK generators shared by all eight
Table 11 on page 54
ADDRESSING THE COE-RAM
ADDRESSING THE FSK-RAM
INDUSTRIAL TEMPERATURE RANGE
for the Coe-RAM address allocation.