82V1068PF8 IDT, Integrated Device Technology Inc, 82V1068PF8 Datasheet - Page 31

• Manufacturer Part Number: 82V1068PF8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 82V1068PF8

• Single Supply Voltage (typ): 3.3V
• Single Supply Voltage (min): 3.135V
• Single Supply Voltage (max): 3.6V
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

IDT82V1068 OCTAL PROGRAMMABLE PCM CODEC
GC6:
GC7:
Sel[3:0] = 0110:
Sel[3:0] = 1110:
Sel[3:0] = 0101:
Sel[3:0] = 1101:
Sel[3:0] = 0100:
Sel[3:0] = 1100:
(In GCI mode, the MCLK frequency as same as the DCL frequency, which is 2.048 MHz or 4.096 MHz, depending on the logic level of
the CI/DOUBLE pin. Refer to
Channel Program Enable, Read/Write (25H/A5H). (This command is available for MPI mode only.)
The Channel Program Enable command is used to specify the channel(s) before Local Commands or a Coe-RAM Commands are used.
This command byte provides one bit per channel to indicate if the corresponding channel will receive Local Commands and Coe-RAM
Commands.
CE[0] = 0:
CE[0] = 1:
CE[1] = 0:
CE[1] = 1:
CE[2] = 0:
CE[2] = 1:
CE[3] = 0:
CE[3] = 1:
CE[4] = 0:
CE[4] = 1:
CE[5] = 0:
CE[5] = 1:
CE[6] = 0:
CE[6] = 1:
CE[7] = 0:
CE[7] = 1:
PCM Data Offset, PCM Clock Slope, Data Mode Select, and A/µ-Law Select, Read/Write (26H/A6H)
The PCM Data Offset bits (DO[2:0]) determine the PCM data transmit/receive time slots will be offset from the Frame Synchronous (FS)
signal by how many BCLK periods. (For MPI mode only)
DO[2:0] = 000:
DO[2:0] = 001:
DO[2:0] = 010:
DO[2:0] = 011:
DO[2:0] = 100:
DO[2:0] = 101:
DO[2:0] = 110:
DO[2:0] = 111:
The CS[2] bit is used to select the clock mode (single or double). If single clock is selected, the data rate will be as same as the BCLK
frequency. If double clock is selected, the data rate will be half of the BCLK frequency. (For MPI mode only)
CS[2] = 0:
CS[2] = 1:
Command
Command
I/O Data
I/O Data
CE[7]
R/W
R/W
b7
b7
LS
1.536 MHz
1.544 MHz
3.072 MHz
3.088 MHz
6.144 MHz
6.176 MHz
Disabled, Channel 1 will not receive Local Commands and Coe-RAM Commands (default);
Enabled, Channel 1 will receive Local Commands and Coe-RAM Commands.
Disabled, Channel 2 will not receive Local Commands and Coe-RAM Commands (default);
Enabled, Channel 2 will receive Local Commands and Coe-RAM Commands.
Disabled, Channel 3 will not receive Local Commands and Coe-RAM Commands (default);
Enabled, Channel 3 will receive Local Commands and Coe-RAM Commands.
Disabled, Channel 4 will not receive Local Commands and Coe-RAM Commands (default);
Enabled, Channel 4 will receive Local Commands and Coe-RAM Commands.
Disabled, Channel 5 will not receive Local Commands and Coe-RAM Commands (default);
Enabled, Channel 5 will receive Local Commands and Coe-RAM Commands.
Disabled, Channel 6 will not receive Local Commands and Coe-RAM Commands (default);
Enabled, Channel 6 will receive Local Commands and Coe-RAM Commands.
Disabled, Channel 7 will not receive Local Commands and Coe-RAM Commands (default);
Enabled, Channel 7 will receive Local Commands and Coe-RAM Commands.
Disabled, Channel 8 will not receive Local Commands and Coe-RAM Commands (default);
Enabled, Channel 8 will receive Local Commands and Coe-RAM Commands.
offset from the FS signal by 0 BCLK period (default);
offset from the FS signal by 1 BCLK period;
offset from the FS signal by 2 BCLK periods;
offset from the FS signal by 3 BCLK periods;
offset from the FS signal by 4 BCLK periods;
offset from the FS signal by 5 BCLK periods;
offset from the FS signal by 6 BCLK periods;
offset from the FS signal by 7 BCLK periods.
single clock is selected (default);
double clock is selected;
“1 Pin Description” on page 7
CE[6]
DMS
b6
b6
0
0
CE[5]
CS[2]
b5
b5
1
1
CE[4]
CS[1]
for further details.)
31
b4
b4
0
0
CE[3]
CS[0]
b3
b3
0
0
DO[2]
CE[2]
b2
b2
1
1
INDUSTRIAL TEMPERATURE RANGE
DO[1]
CE[1]
b1
b1
0
1
CE[0]
DO[0]
b0
b0
1
0