MT48H4M16LFB4-75 Micron Technology Inc, MT48H4M16LFB4-75 Datasheet - Page 32

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MT48H4M16LFB4-75

Manufacturer Part Number
MT48H4M16LFB4-75
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet

Specifications of MT48H4M16LFB4-75

Organization
4Mx16
Density
64Mb
Address Bus
14b
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
50mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant

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Concurrent Auto Precharge
READ with Auto Precharge
Figure 27:
PDF: 09005aef8237ed98, Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. B 10/06 EN
READ with Auto Precharge Interrupted by a READ
Note:
1. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
2. Interrupted by a WRITE (with or without auto precharge): When a WRITE to bank m
Micron SDRAM devices support concurrent auto precharge, which allows an access
command (READ or WRITE) to another bank while an access command with auto
precharge enabled is executing. Four cases where concurrent auto precharge occurs are
defined below.
Internal
States
rupt a READ on bank n, two or three clocks later, depending on CAS latency. The pre-
charge to bank n will begin when the READ to bank m is registered (Figure 27).
registers, a READ on bank n will be interrupted. DQM should be used two clocks prior
to the WRITE command to prevent bus contention. The precharge to bank n will
begin when the WRITE to bank m is registered (Figure 28 on page 33).
DQM is LOW.
COMMAND
ADDRESS
BANK m
BANK n
CLK
DQ
Page Active
T0
NOP
READ - AP
BANK n,
Page Active
BANK n
COL a
T1
READ with Burst of 4
CAS Latency = 3 (BANK n)
32
T2
NOP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
BANK m,
READ - AP
T3
BANK m
COL d
Interrupt Burst, Precharge
CAS Latency = 3 (BANK m)
READ with Burst of 4
64Mb: 4 Meg x 16 Mobile SDRAM
T4
NOP
D
OUT
a
t
RP - BANK n
T5
NOP
D
a + 1
OUT
T6
NOP
©2006 Micron Technology, Inc. All rights reserved.
D
OUT
d
DON’T CARE
Idle
T7
NOP
t RP - BANK m
Precharge
D
d + 1
OUT

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