MT48H4M16LFB4-75 Micron Technology Inc, MT48H4M16LFB4-75 Datasheet - Page 27

• Manufacturer Part Number: MT48H4M16LFB4-75
• Manufacturer: Micron Technology Inc
• Type: SDRAMr

Specifications of MT48H4M16LFB4-75

• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 50mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Figure 19:
Figure 20:
PDF: 09005aef8237ed98, Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. B 10/06 EN
Random WRITE Cycles
WRITE-to-READ
Note:
Note:
either the last of a burst of two or the last desired of a longer burst. Following the
PRECHARGE command, a subsequent command to the same bank cannot be issued
until
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvan-
tage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length bursts.
Fixed-length WRITE bursts can be truncated with the BURST TERMINATE command.
When truncating a WRITE burst, the input data applied coincident with the BURST
TERMINATE command will be ignored. The last data written (provided that DQM is
LOW at that time) will be the input data applied one clock previous to the BURST
TERMINATE command. This is shown in Figure 23 on page 29, where data n is the last
desired data element of a longer burst.
COMMAND
COMMAND
ADDRESS
ADDRESS
Each WRITE command may be issued to any bank. DQM is LOW.
The WRITE command may be issued to any bank, and the READ command may be issued
to any bank. DQM is LOW. CAS latency = 2 for illustration.
CLK
t
CLK
DQ
DQ
RP is met.
WRITE
BANK,
COL n
BANK,
WRITE
COL n
D
T0
n
D
IN
T0
n
IN
n + 1
NOP
T1
D
WRITE
BANK,
COL a
IN
T1
D
a
IN
BANK,
COL b
READ
T2
BANK,
WRITE
COL x
D
T2
x
IN
27
DON’T CARE
T3
NOP
WRITE
BANK,
COL m
T3
D
m
IN
NOP
D
T4
OUT
Micron Technology, Inc., reserves the right to change products or specifications without notice.
b
DON’T CARE
64Mb: 4 Meg x 16 Mobile SDRAM
NOP
T5
D
b + 1
OUT
©2006 Micron Technology, Inc. All rights reserved.