MT48H4M16LFB4-75 Micron Technology Inc, MT48H4M16LFB4-75 Datasheet - Page 23
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MT48H4M16LFB4-75
Manufacturer Part Number
MT48H4M16LFB4-75
Description
Manufacturer
Micron Technology Inc
Type
SDRAMr
Datasheet
1.MT48H4M16LFB4-75.pdf
(64 pages)
Specifications of MT48H4M16LFB4-75
Organization
4Mx16
Density
64Mb
Address Bus
14b
Maximum Clock Rate
133MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
50mA
Pin Count
54
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT48H4M16LFB4-75 IT:H
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Company:
Part Number:
MT48H4M16LFB4-75 IT:H TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Company:
Part Number:
MT48H4M16LFB4-75:H
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Part Number:
MT48H4M16LFB4-75:H
Manufacturer:
MICRON
Quantity:
20 000
Company:
Part Number:
MT48H4M16LFB4-75:H TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Company:
Part Number:
MT48H4M16LFB4-75IT:H
Manufacturer:
ISSI
Quantity:
171
Figure 12:
Figure 13:
PDF: 09005aef8237ed98, Source: 09005aef8237ed68
64mb_x16_Mobile SDRAM_Y24L_2.fm - Rev. B 10/06 EN
READ-to-WRITE
READ-to-WRITE with Extra Clock Cycle
Note:
Note:
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvan-
tage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length bursts.
COMMAND
COMMAND
ADDRESS
ADDRESS
A CAS latency of three is used for illustration. The READ command may be issued to any
bank, and the WRITE command may be issued to any bank. If a burst of one is used, then
DQM is not required.
A CAS latency of three is used for illustration. The READ command may be issued to any
bank, and the WRITE command may be issued to any bank.
DQM
DQM
CLK
CLK
DQ
DQ
BANK,
COL n
T0
BANK,
T0
COL n
READ
READ
T1
T1
NOP
NOP
T2
T2
NOP
NOP
23
T3
T3
NOP
NOP
D
OUT
t HZ
t HZ
D
t CK
OUT
n
n
DON’T CARE
T4
BANK,
T4
COL b
Micron Technology, Inc., reserves the right to change products or specifications without notice.
WRITE
NOP
D
IN
b
t
DS
64Mb: 4 Meg x 16 Mobile SDRAM
DON’T CARE
T5
BANK,
COL b
WRITE
D
IN
b
t
DS
©2006 Micron Technology, Inc. All rights reserved.