IDT82V3285DQGT IDT, Integrated Device Technology Inc, IDT82V3285DQGT Datasheet - Page 72
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IDT82V3285DQGT
Manufacturer Part Number
IDT82V3285DQGT
Description
IC PLL WAN STRATUM 100-TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
PLL Clock Generatorr
Datasheet
1.IDT82V3285DQGT.pdf
(143 pages)
Specifications of IDT82V3285DQGT
Input
CMOS, LVDS, PECL, TTL
Output
CMOS, LVDS, PECL, TTL
Frequency - Max
622.08MHz
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
100-TQFP, 100-VQFP
Frequency-max
622.08MHz
Function
Wan PLL
Operating Temperature (max)
85C
Operating Temperature (min)
-40C
Package Type
TQFP
Pin Count
100
Mounting
Surface Mount
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
82V3285DQGT
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INTERRUPTS3_STS - Interrupt Status 3
INTERRUPTS1_ENABLE_CNFG - Interrupt Control 1
Programming Information
IDT82V3285
Address: 0FH
Type: Read / Write
Default Value: 11X10000
Address: 10H
Type: Read / Write
Default Value: 00000000
EX_SYNC_ALARM
3 - 0
7 - 6
5 - 2
0 -1
Bit
Bit
7
6
5
4
7
-
7
EX_SYNC_ALARM
INPUT_TO_T4
Name
T4_STS
Name
INn
-
-
-
-
T4_STS
6
-
6
Reserved.
This bit controls whether the interrupt is enabled to be reported on the INT_REQ pin when the input clock validity changes (from
‘valid’ to ‘invalid’ or from ‘invalid’ to ‘valid’), i.e., when the corresponding INn bit (b5~2, 0DH) is ‘1’. Here n is any one of 4 to 1.
0: Disabled. (default)
1: Enabled.
Reserved
This bit indicates whether an external sync alarm is raised; i.e., whether there is a transition from ‘0’ to ‘1’ on the
EX_SYNC_ALARM_MON bit (b7, 52H).
0: Not raised.
1: Raised. (default)
This bit is cleared by writing a ‘1’.
This bit indicates the T4 DPLL locking status changes (from ‘locked’ to ‘unlocked’ or from ‘unlocked’ to ‘locked’); i.e., whether
there is a transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the T4_DPLL_LOCK bit (b6, 52H).
0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
Reserved.
This bit indicates whether all the input clocks for T4 path change to be unqualified; i.e., whether the
HIGHEST_PRIORITY_VALIDATED[3:0] bits (b7~4, 4EH) are set to ‘0000’ when these bits are available for T4 path.
0: Has not changed.
1: Has changed. (default)
This bit is cleared by writing a ‘1’.
Reserved.
IN4
5
5
-
INPUT_TO_T4
IN3
4
4
72
IN2
3
3
-
Description
Description
IN1
2
2
-
1
-
1
-
April 11, 2007
0
0
-
WAN PLL
-
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