IDT82V3285DQGT IDT, Integrated Device Technology Inc, IDT82V3285DQGT Datasheet - Page 61

• Manufacturer Part Number: IDT82V3285DQGT
• Description: IC PLL WAN STRATUM 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3285DQGT

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3285DQGT

Table 41: Register List and Map (Continued)
7.2
7.2.1
ID[7:0] - Device ID 1
Programming Information
IDT82V3285
Address
Address: 00H
Type: Read
Default Value: 10001000
(Hex)
6E
7A
7B
7C
7D
6F
70
71
72
73
74
78
7 - 0
Bit
ID7
OUT2_FREQ_CNFG - Output Clock 2
Frequency Configuration
OUT3_FREQ_CNFG - Output Clock 3
Frequency Configuration
OUT4_FREQ_CNFG - Output Clock 4
Frequency Configuration
OUT5_FREQ_CNFG - Output Clock 5
Frequency Configuration
OUTPUT_INV2 - Output Clock 4 & 5
Invert Configuration
OUTPUT_INV1 - Output Clock 1 ~ 3
Invert Configuration
FR_MFR_SYNC_CNFG - Frame Sync
& Multiframe Sync Output Configura-
tion
PHASE_MON_PBO_CNFG - Phase
Transient Monitor & PBO Configura-
tion
PHASE_OFFSET[7:0]_CNFG - Phase
Offset Configuration 1
PHASE_OFFSET[9:8]_CNFG - Phase
Offset Configuration 2
SYNC_MONITOR_CNFG - Sync Mon-
itor Configuration
SYNC_PHASE_CNFG - Sync Phase
Configuration
7
REGISTER DESCRIPTION
GLOBAL CONTROL REGISTERS
Register Name
ID[7:0]
Name
ID6
6
Refer to the description of the ID[15:8] bits (b7~0, 01H).
ID5
IN_2K_4K_
_WINDOW
IN_NOISE
PH_OFFS
5
8K_INV
ET_EN
Bit 7
-
-
Synchronization Configuration Registers
PBO & Phase Offset Control Registers
OUT2_PATH_SEL[3:0]
OUT3_PATH_SEL[3:0]
OUT4_PATH_SEL[3:0]
OUT5_PATH_SEL[3:0]
8K_EN
Bit 6
-
-
-
-
ID4
SYNC_MON_LIMT[2:0]
4
PH_MON_
2K_EN
Bit 5
EN
61
-
-
-
2K_8K_PU
OUT3_INV OUT2_INV OUT1_INV
PH_MON_
L_POSITI
ID3
PBO_EN
3
Bit 4
PH_OFFSET[7:0]
ON
Description
-
-
8K_INV
Bit 3
-
-
-
ID2
2
PH_TR_MON_LIMT[3:0]
8K_PUL
OUT2_DIVIDER[3:0]
OUT3_DIVIDER[3:0]
OUT4_DIVIDER[3:0]
OUT5_DIVIDER[3:0]
Bit 2
-
-
-
OUT5_INV OUT4_INV
2K_INV
ID1
1
Bit 1
PH_OFFSET[9:8]
SYNC_PH1[1:0]
-
-
2K_PUL
Bit 0
-
April 11, 2007
ID0
0
WAN PLL
Reference
P 121
P 123
P 124
P 125
P 126
P 126
P 118
P 119
P 120
P 121
P 122
P 124
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