IDT82V3285DQGT IDT, Integrated Device Technology Inc, IDT82V3285DQGT Datasheet - Page 65

• Manufacturer Part Number: IDT82V3285DQGT
• Description: IC PLL WAN STRATUM 100-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: PLL Clock Generatorr

Specifications of IDT82V3285DQGT

• Input: CMOS, LVDS, PECL, TTL
• Output: CMOS, LVDS, PECL, TTL
• Frequency - Max: 622.08MHz
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Frequency-max: 622.08MHz
• Function: Wan PLL
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Package Type: TQFP
• Pin Count: 100
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 82V3285DQGT

INPUT_MODE_CNFG - Input Mode Configuration
Programming Information
IDT82V3285
Address: 09H
Type: Read / Write
Default Value: 10100XX0
AUTO_EXT_SY
4 - 3
Bit
7
6
5
2
1
0
NC_EN
7
AUTO_EXT_SYNC_EN Refer to the description of the EXT_SYNC_EN bit (b6, 09H).
PH_ALARM_TIMEOUT
REVERTIVE_MODE
SYNC_FREQ[1:0]
MASTER_SLAVE
IN_SONET_SDH
EXT_SYNC_EN
EXT_SYNC_EN
Name
6
This bit, together with the AUTO_EXT_SYNC_EN bit (b7, 09H), determines whether EX_SYNC1 is enabled to synchronize
the frame sync output signals.
This bit determines how to clear the phase lock alarm.
0: The phase lock alarm will be cleared when a ‘1’ is written to the corresponding INn_PH_LOCK_ALARM bit (b4/0, 44H &
45H & 48H).
1: The phase lock alarm will be cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X MULTI_FACTOR[1:0]
(b7~6, 08H) in seconds) which starts from when the alarm is raised. (default)
These bits set the frequency of the frame sync signal input on the EX_SYNC1 pin.
00: 8 kHz (default)
01: 8 kHz.
10: 4 kHz.
11: 2 kHz.
This bit selects the SDH or SONET network type.
0: SDH. The DPLL required clock is 2.048 MHz when the IN_FREQ[3:0] bits (b3~0, 16H & 17H & 19H) are ‘0001’; the T0/T4
DPLL output from the 16E1/16T1 path is 16E1.
1: SONET. The DPLL required clock is 1.544 MHz when the IN_FREQ[3:0] bits (b3~0, 16H & 17H & 19H) are ‘0001’; the T0/
T4 DPLL output from the 16E1/16T1 path is 16T1.
The default value of this bit is determined by the SONET/SDH pin during reset.
This bit is read only. It indicates the value of the MS/SL pin.
This bit selects Revertive or Non-Revertive switch for T0 path.
0: Non-Revertive switch. (default)
1: Revertive switch.
Its default value is determined by the MS/SL pin during reset.
AUTO_EXT_SYNC_EN
PH_ALARM_TI
MEOUT
don’t-care
5
0
1
SYNC_FREQ1
EXT_SYNC_EN
4
0
1
1
65
SYNC_FREQ0
3
Enabled if the T0 selected input clock is IN5; otherwise, disabled.
Description
IN_SONET_SD
H
2
Synchronization
Disabled (default)
Enabled
MASTER_SLAV
E
1
REVERTIVE_M
April 11, 2007
ODE
WAN PLL
0