ICS8624BYLF IDT, Integrated Device Technology Inc, ICS8624BYLF Datasheet - Page 8

• Manufacturer Part Number: ICS8624BYLF
• Description: IC BUFFER ZD 1-5 HSTL 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Distribution, Multiplexer , Zero Delay Bufferr

Specifications of ICS8624BYLF

• Pll: Yes with Bypass
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: HSTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Frequency - Max: 700MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 700MHz
• Number Of Elements: 1
• Supply Current: 120mA
• Pll Input Freq (min): 31.25MHz
• Pll Input Freq (max): 700MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: LQFP
• Output Frequency Range: Up to 700MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 8624BYLF

ICS8624 Data Sheet
Parameter Measurement Information, continued
Output Rise/Fall Time
Application Information
Power Supply Filtering Technique
To achieve optimum jitter performance, power supply isolation is
required. To achieve optimum jitter performance, power supply
isolation is required. The ICS8624 provides separate power supplies
to isolate any high switching noise from the outputs to the internal
PLL. V
power supply plane through vias, and 0.01µF bypass capacitors
should be used for each pin. Figure 1 illustrates this for a generic V
pin and also shows that V
along with a 10µF bypass capacitor be connected to the V
ICS8624BY REVISION E OCTOBER 6, 2009
nQ[0:4]
Q[0:4]
DD,
V
V
OX
DDA
20%
and V
DDO
80%
t
R
DDA
should be individually connected to the
requires that an additional 10Ω resistor
80%
t
F
20%
V
DDA
SW I N G
pin.
DD
8
Propagation Delay
nQ[0:4]
nCLK0,
nCLK1
Q[0:4]
CLK0,
CLK1
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
Figure 1. Power Supply Filtering
t
PD
V
V
DDA
DD
©2009 Integrated Device Technology, Inc.
.01µF
.01µF
3.3V
10Ω
10µF