ICS8624BYLF IDT, Integrated Device Technology Inc, ICS8624BYLF Datasheet - Page 6

• Manufacturer Part Number: ICS8624BYLF
• Description: IC BUFFER ZD 1-5 HSTL 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Distribution, Multiplexer , Zero Delay Bufferr

Specifications of ICS8624BYLF

• Pll: Yes with Bypass
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: HSTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Frequency - Max: 700MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 700MHz
• Number Of Elements: 1
• Supply Current: 120mA
• Pll Input Freq (min): 31.25MHz
• Pll Input Freq (max): 700MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: LQFP
• Output Frequency Range: Up to 700MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 8624BYLF

ICS8624 Data Sheet
AC Electrical Characteristics
Table 6A. AC Characteristics, V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as the time difference between the input reference clock and the averaged feedback input signal across all conditions, when
the PLL is locked and the input reference frequency is stable.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential
cross points.
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Characterized at VCO frequency of 622MHz.
Table 6B. AC Characteristics, V
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
Table 6C. AC Characteristics, V
For NOTES, see Table 6A above.
ICS8624BY REVISION E OCTOBER 6, 2009
Symbol
f
t
t(Ø)
tsk(o)
tjit(cc)
tjit(θ)
t
t
t
Symbol
tjit(cc)
Symbol
f
t
t(Ø)
tsk(o)
tjit(cc)
tjit(θ)
t
t
t
MAX
PD
L
R
PW
MAX
PD
L
R
PW
/ t
/ t
F
F
Static Phase Offset; NOTE 2, 5
Output Skew; NOTE 3, 5
Static Phase Offset; NOTE 2, 5
Output Skew; NOTE 3, 5
Parameter
Output Frequency
Propagation Delay; NOTE 1
Cycle-to-Cycle Jitter; NOTE 5, 6
Phase Jitter; NOTE 4, 5, 6
PLL Lock Time
Output Rise/Fall Time
Output Pulse Width
Parameter
Cycle-to-Cycle Jitter; NOTE 1
Parameter
Output Frequency
Propagation Delay; NOTE 1
Cycle-to-Cycle Jitter; NOTE 5, 6
Phase Jitter; NOTE 4, 5, 6
PLL Lock Time
Output Rise/Fall Time
Output Pulse Width
DD
DD
DD
= 3.3V ± 5%, V
= 3.3V ± 10%, V
= 3.3V ± 5%, V
20% to 80% @ 50MHz
20% to 80% @ 50MHz
Test Conditions
PLL_SEL = 3.3V
Test Conditions
Test Conditions
PLL_SEL = 3.3V
DDO
DDO
ƒ ≤ 700MHz
ƒ ≤ 700MHz
DDO
= 1.8V ± 0.2V, T
= 1.5V to 1.6V, T
= 1.8V ± 0.2V, T
6
A
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
A
A
= 0°C to 70°C
= 0°C to 70°C
= 0°C to 70°C
t
t
Minimum
cycle
Minimum
Minimum
cycle
-100
-100
300
300
3.2
3.2
/2 - 85
/2 - 95
Typical
Typical
Typical
t
t
cycle
cycle
©2009 Integrated Device Technology, Inc.
/2
/2
t
t
cycle
cycle
Maximum
Maximum
Maximum
700
100
±50
700
700
150
±50
700
4.4
4.4
25
25
35
35
25
/2 + 85
/2 + 95
1
1
Units
Units
Units
MHz
MHz
ms
ms
ns
ps
ps
ps
ps
ps
ps
ps
ns
ps
ps
ps
ps
ps
ps