ICS8624BYLF IDT, Integrated Device Technology Inc, ICS8624BYLF Datasheet - Page 2

• Manufacturer Part Number: ICS8624BYLF
• Description: IC BUFFER ZD 1-5 HSTL 32-LQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: HiPerClockS™r
• Type: Fanout Distribution, Multiplexer , Zero Delay Bufferr

Specifications of ICS8624BYLF

• Pll: Yes with Bypass
• Input: HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: HSTL
• Number Of Circuits: 1
• Ratio - Input:output: 2:5
• Differential - Input:output: Yes/Yes
• Frequency - Max: 700MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Frequency-max: 700MHz
• Number Of Elements: 1
• Supply Current: 120mA
• Pll Input Freq (min): 31.25MHz
• Pll Input Freq (max): 700MHz
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: LQFP
• Output Frequency Range: Up to 700MHz
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (max): 3.465V
• Operating Temperature Classification: Commercial
• Pin Count: 32
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 8624BYLF

ICS8624 Data Sheet
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
ICS8624BY REVISION E OCTOBER 6, 2009
Symbol
C
R
R
Number
IN
PULLUP
PULLDOWN
12, 13,
16, 17,
28, 29
14, 15
24, 25
18, 19
20, 21
22, 23
26, 27
9, 32
1, 2
10
11
30
31
3
4
5
6
7
8
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
SEL0, SEL1
CLK_SEL
PLL_SEL
nQ0, Q0
nQ1, Q1
nQ2, Q2
nQ3, Q3
nQ4, Q4
nFB_IN
nCLK0
nCLK1
FB_IN
Name
CLK0
CLK1
V
V
GND
V
MR
DDO
DDA
DD
Output
Output
Output
Output
Output
Power
Power
Power
Power
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Pullup
Pullup
Pullup
Test Conditions
Description
Determines the input and output frequency range noted in Table 3A.
LVCMOS / LVTTL interface levels.
Non-inverting differential clock input.
Inverting differential clock input.
Non-inverting differential clock input.
Inverting differential clock input.
Clock select input. When HIGH, selects CLK1, nCLK1. When LOW, selects CLK0,
nCLK0. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Qx to go low and the inverted outputs nQx to go high.
When logic LOW, the internal dividers and the outputs are enabled.
LVCMOS / LVTTL interface levels.
Core supply pins.
Inverting differential feedback input to phase detector for regenerating clocks with
“Zero Delay.”
Non-inverted differential feedback input to phase detector for regenerating clocks
with “Zero Delay.”
Power supply ground.
Differential output pair. HSTL interface levels.
Output supply pins.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Differential output pair. HSTL interface levels.
Analog supply pin.
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS/LVTTL interface levels.
2
LOW SKEW, 1-TO-5 DIFFERENTIAL-TO-HSTL ZERO DELAY BUFFER
Minimum
©2009 Integrated Device Technology, Inc.
Typical
51
51
4
Maximum
Units
k
k
pF
Ω
Ω