SI5317A-C-GM Silicon Laboratories Inc, SI5317A-C-GM Datasheet - Page 25

• Manufacturer Part Number: SI5317A-C-GM
• Description: IC CLK JITTER CLEANR PROG 36QFN
• Manufacturer: Silicon Laboratories Inc
• Type: Jitter Cleanerr
• Series: Si5317r

Specifications of SI5317A-C-GM

• Package / Case: 36-QFN
• Pll: Yes with Bypass
• Input: Clock, Crystal
• Output: CML, CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: Yes/Yes
• Frequency - Max: 710MHz
• Divider/multiplier: No/No
• Voltage - Supply: 1.71 V ~ 3.63 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Frequency-max: 710MHz
• Termination Style: SMD/SMT
• Output Format: LVPECL
• Dimensions: 5 mm W x 7 mm L x 1.85 mm H
• Minimum Operating Temperature: - 40 C
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Product: XO
• Frequency: 10 MHz to 945 MHz
• Frequency Stability: +/- 20 PPM
• Supply Voltage: 3.3 Volts
• Height: 1.85 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 336-1923

4. High-Speed I/O
4.1. Input Clock Buffer
The Si5317 provides differential inputs for the CKIN clock input. This input is internally biased to a common mode
voltage (see Table 2, “DC Characteristics”) and can be driven by either a single-ended or differential source. No
additional external bias is required. Figure 7 through Figure 10 show typical interface circuits for LVPECL, CML,
LVDS, or CMOS input clocks. Note that the jitter generation improves for higher levels on CKINn within the limits in
Table 4, “AC Characteristics”.
AC coupling the input clocks is recommended because it removes any issue with common mode input voltages.
DC coupling is acceptable if the device driving the Si5317 meets all of the input clock requirements, including the
input common mode range and the peak-to-peak swing specifications. Figure 7 and Figure 8 shows various
examples of different input termination arrangements. Unused inputs can be left unconnected.
Driver
LVPECL
Driver
Figure 8. Single-ended LVPECL Termination
Figure 7. Differential LVPECL Termination
130
82


130
82


3.3 V
3.3 V
130
82


C
Rev. 1.1
C
C
C
40 k
40 k
40 k
40 k
Si5317
Si5317


CKIN +
CKIN
CKIN +
CKIN
300
300
_
_


±
±
V
ICM
V
ICM
Si5317
25