74HCT4046AD,112 NXP Semiconductors, 74HCT4046AD,112 Datasheet - Page 3

• Manufacturer Part Number: 74HCT4046AD,112
• Description: IC PHASE LOCK LOOP W/VCO 16SOIC
• Manufacturer: NXP Semiconductors
• Type: Phase Lock Loop (PLL)r
• Series: 74HCTr

Specifications of 74HCT4046AD,112

• Number Of Circuits: 1
• Package / Case: 16-SOIC (3.9mm Width)
• Pll: Yes
• Input: Clock
• Output: Clock
• Ratio - Input:output: 2:3
• Differential - Input:output: No/No
• Frequency - Max: 19MHz
• Divider/multiplier: No/No
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Frequency-max: 19MHz
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Input Level: CMOS
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 4.5 V to 5.5 V
• Output Level: CMOS
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-1547-5; 74HCT4046AD; 933809570112

Philips Semiconductors
The frequency capture range (2f
frequency range of input signals on which the PLL will lock
if it was initially out-of-lock. The frequency lock range
(2f
which the loop will stay locked if it was initially in lock. The
capture range is smaller or equal to the lock range.
With PC1, the capture range depends on the low-pass
filter characteristics and can be made as large as the lock
range.
This configuration retains lock even with very noisy input
signals. Typical behaviour of this type of phase
comparator is that it can lock to input frequencies close to
the harmonics of the VCO centre frequency.
Phase comparator 2 (PC2)
This is a positive edge-triggered phase and frequency
detector. When the PLL is using this comparator, the loop
is controlled by positive signal transitions and the duty
factors of SIG
comprises two D-type flip-flops, control-gating and a
3-state output stage. The circuit functions as an up-down
counter (Fig.5) where SIG
COMP
assuming ripple (f
is:
where V
V
The phase comparator gain is:
V
SIG
for the PC2 loop locked at f
When the frequencies of SIG
the phase of SIG
output driver at PC2
corresponding to the phase difference (
the phase of SIG
is held “ON”.
When the frequency of SIG
COMP
the input signal cycle time, and for the remainder of the
cycle both n and p- type drivers are ”OFF” (3-state). If the
SIG
it is the n-type driver that is held “ON” for most of the cycle.
Subsequently, the voltage at the capacitor (C2) of the
low-pass filter connected to PC2
1997 Nov 25
DEMOUT
DEMOUT
Phase-locked-loop with VCO
L
V
) is defined as the frequency range of input signals on
IN
IN
DEMOUT
and COMP
frequency is lower than the COMP
IN
IN
DEMOUT
, the p-type output driver is held “ON” for most of
a down-count. The transfer function of PC2,
= V
is the resultant of the initial phase differences of
PC2OUT
IN
=
and COMP
is the demodulator output at pin 10;
V
---------- -
IN
IN
4
IN
r
CC
= f
leads that of COMP
lags that of COMP
as shown in Fig.8. Typical waveforms
OUT
(via low-pass filter).
i
) is suppressed,
SIGIN
is held “ON” for a time
IN
IN
o
IN
causes an up-count and
IN
are shown in Fig.9.
–
is higher than that of
are not important. PC2
K
and COMP
COMPIN
OUT
c
p
) is defined as the
=
varies until the signal
V
---------- - V r .
4
IN
CC
IN
, the n-type driver
IN
DEMOUT
, the p-type
IN
frequency, then
are equal but
). When
3
and comparator inputs are equal in both phase and
frequency. At this stable point the voltage on C2 remains
constant as the PC2 output is in 3-state and the VCO input
at pin 9 is a high impedance. Also in this condition, the
signal at the phase comparator pulse output (PCP
HIGH level and so can be used for indicating a locked
condition.
Thus, for PC2, no phase difference exists between
SIG
VCO. Moreover, the power dissipation due to the low-pass
filter is reduced because both p and n-type drivers are
“OFF” for most of the signal input cycle. It should be noted
that the PLL lock range for this type of phase comparator
is equal to the capture range and is independent of the
low-pass filter. With no signal present at SIG
VCO adjusts, via PC2, to its lowest frequency.
Phase comparator 3 (PC3)
This is a positive edge-triggered sequential phase detector
using an RS-type flip-flop. When the PLL is using this
comparator, the loop is controlled by positive signal
transitions and the duty factors of SIG
not important. The transfer characteristic of PC3,
assuming ripple (f
is:
where V
V
The phase comparator gain is:
The average output from PC3, fed to the VCO via the
low-pass filter and seen at the demodulator output at
pin 10 (V
of SIG
waveforms for the PC3 loop locked at f
Fig.11.
The phase-to-output response characteristic of PC3
(Fig.10) differs from that of PC2 in that the phase angle
between SIG
360 and is 180 at the centre frequency. Also PC3 gives
a greater voltage swing than PC2 for input phase
differences but as a consequence the ripple content of the
VCO input signal is higher. The PLL lock range for this type
of phase comparator and the capture range are dependent
on the low-pass filter. With no signal present at SIG
VCO adjusts, via PC3, to its lowest frequency.
DEMOUT
V
IN
DEMOUT
and COMP
IN
DEMOUT
and COMP
DEMOUT
= V
PC3OUT
IN
=
and COMP
is the demodulator output at pin 10;
), is the resultant of the phase differences
V
---------- -
2
IN
r
CC
= f
over the full frequency range of the
IN
(via low-pass filter).
i
) is suppressed,
as shown in Fig.10. Typical
SIGIN
IN
–
74HC/HCT4046A
varies between 0 and
K
COMPIN
p
=
Product specification
V
---------- - V r .
2
IN
CC
o
and COMP
are shown in
IN
the
OUT
IN
IN
) is a
are
the