ICS8543BGLF IDT, Integrated Device Technology Inc, ICS8543BGLF Datasheet

IC FANOUT BUFF DIFF-LVDS 20TSSOP

ICS8543BGLF

Manufacturer Part Number
ICS8543BGLF
Description
IC FANOUT BUFF DIFF-LVDS 20TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Fanout Buffer (Distribution), Multiplexerr
Series
HiPerClockS™r
Datasheet

Specifications of ICS8543BGLF

Number Of Circuits
1
Ratio - Input:output
2:4
Differential - Input:output
Yes/Yes
Input
CML, HCSL, LVDS, LVHSTL, LVPECL, SSTL
Output
LVDS
Frequency - Max
800MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
20-TSSOP
Frequency-max
800MHz
Number Of Clock Inputs
2
Mode Of Operation
Differential
Output Frequency
800MHz
Output Logic Level
LVDS
Operating Supply Voltage (min)
3.135V
Operating Supply Voltage (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Package Type
TSSOP
Operating Temp Range
0C to 70C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
20
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
800-1186
800-1186-5
800-1186
8543BGLF

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ICS8543BGLF
Manufacturer:
IDT
Quantity:
755
Part Number:
ICS8543BGLFT
Manufacturer:
IDT
Quantity:
20 000
General Description
The ICS8543 is a low skew, high performance 1-to-4
Differential-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage
Differential Signaling (LVDS) the ICS8543 provides a low power, low
noise, solution for distributing clock signals over controlled
impedances of 100Ω. The ICS8543 has two selectable clock inputs.
The CLK, nCLK pair can accept most standard differential input
levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL
input levels. The clock enable is internally synchronized to eliminate
runt pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics make the
ICS8543 ideal for those applications demanding well defined
performance and repeatability.
ICS8543BG REVISION E DECEMBER 17, 2010
Block Diagram
CLK_SEL
CLK_EN
nPCLK
PCLK
nCLK
CLK
OE
Pullup
Pulldown
Pullup
Pulldown
Pullup
Pulldown
Pullup
0
1
0
1
Low Skew, 1-to-4,
Differential-to-LVDS Fanout Buffer
D
LE
Q
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
1
Features
Four differential LVDS output pairs
Selectable differential CLK, nCLK or LVPECL clock inputs
CLK, nCLK pair can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
PCLK, nPCLK pair can accept the following differential input
levels: LVPECL, CML, SSTL
Maximum output frequency: 800MHz
Translates any single-ended input signals to LVDS levels with
resistor bias on nCLK input
Additive phase jitter, RMS: 0.164ps (typical)
Output skew: 40ps (maximum)
Part-to-part skew: 500ps (maximum)
Propagation delay: 2.6ns (maximum)
Full 3.3V supply mode
0°C to 70°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Pin Assignment
6.5mm x 4.4mm x 0.925
CLK_SEL
CLK_EN
nPCLK
PCLK
nCLK
GND
GND
CLK
V
20-Lead TSSOP
OE
DD
package body
G Package
Top View
ICS8543
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
©2010 Integrated Device Technology, Inc.
Q0
V
Q1
nQ1
nQ2
Q3
nQ0
Q2
nQ3
DD
mm
DATA SHEET
ICS8543

Related parts for ICS8543BGLF

ICS8543BGLF Summary of contents

Page 1

Low Skew, 1-to-4, Differential-to-LVDS Fanout Buffer General Description The ICS8543 is a low skew, high performance 1-to-4 Differential-to-LVDS Clock Fanout Buffer. Utilizing Low Voltage Differential Signaling (LVDS) the ICS8543 provides a low power, low noise, solution for distributing clock signals ...

Page 2

ICS8543 Data Sheet Table 1. Pin Descriptions Number Name GND Power 2 CLK_EN Input 3 CLK_SEL Input 4 CLK Input 5 nCLK Input 6 PCLK Input 7 nPCLK Input 8 OE Input 10 Power DD ...

Page 3

ICS8543 Data Sheet Function Tables Table 3A. Control Input Function Table OE CLK_EN After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock ...

Page 4

ICS8543 Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those ...

Page 5

ICS8543 Data Sheet Table 4C. Differential DC Characteristics, V Symbol Parameter CLK I Input High Current IH nCLK CLK I Input Low Current IL nCLK V Peak-to-Peak Voltage; NOTE 1 PP Common Mode Input Voltage; V CMR NOTE 1, 2 ...

Page 6

ICS8543 Data Sheet AC Electrical Characteristics Table 5. AC Characteristics Symbol Parameter f Maximum Output Frequency MAX t Propagation Delay; NOTE 1 PD Buffer Additive Phase Jitter, RMS; tjit refer to Additive Phase Jitter Section tsk(o) Output Skew; ...

Page 7

ICS8543 Data Sheet Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase ...

Page 8

ICS8543 Data Sheet Parameter Measurement Information V DD 3.3V±5% POWER SUPPLY LVDS + Float GND – 3.3V LVDS Output Load AC Test Circuit V DD nQ[0:3] V Cross Points OD Q[0: GND Differential Output Level Par t 1 ...

Page 9

ICS8543 Data Sheet Parameter Measurement Information, continued nQ[0:3] 80% 20% Q[0: Output Rise/Fall Time V DD LVDS DC Input ➤ Offset Voltage Setup 3.3V±5% POWER SUPPLY LVDS t _ Float GND DC Inpu + High Impedance Leakage Current ...

Page 10

ICS8543 Data Sheet Parameter Measurement Information, continued V DD LVDS DC Input Output Short Circuit Current Setup Applications Information Wiring the Differential Input to Accept Single-Ended Levels Figure 2 shows how a differential input can be wired to accept single ...

Page 11

ICS8543 Data Sheet 3.3V Differential Clock Input Interface The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both V SWING and V input requirements. Figures show interface CMR examples for the CLK/nCLK input ...

Page 12

ICS8543 Data Sheet 3.3V LVPECL Clock Input Interface The PCLK/nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both V and V SWING V input requirements. Figures show interface examples CMR for the PCLK/nPCLK input driven by ...

Page 13

ICS8543 Data Sheet Recommendations for Unused Input and Output Pins Inputs: CLK/nCLK I NPUTS For applications not requiring the use of the differential input, both CLK and nCLK can be left floating. Though not required, but for additional protection, a ...

Page 14

ICS8543 Data Sheet Power Considerations This section provides information on power dissipation and junction temperature for the ICS8543. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS8543 is the sum of the ...

Page 15

ICS8543 Data Sheet Reliability Information Table 7. θ vs. Air Flow Table for a 20 Lead TSSOP JA Linear Feet per Minute Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ...

Page 16

... ICS8543BGLF 8543BGLFT ICS8543BGLF NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use ...

Page 17

ICS8543 Data Sheet Revision History Sheet Rev Table Page Description of Change A T4E 5 In the Updated Figure 1, CLK_EN Timing Diagram Updated Figure 1, CLK_EN Timing Diagram. 1 Features section, Bullet 6 to ...

Page 18

ICS8543 Data Sheet We’ve Got Your Timing Solution 6024 Silver Creek Valley Road Sales 800-345-7015 (inside USA) San Jose, California 95138 +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to ...

Related keywords