ICS8543BGLF IDT, Integrated Device Technology Inc, ICS8543BGLF Datasheet - Page 17

• Manufacturer Part Number: ICS8543BGLF
• Description: IC FANOUT BUFF DIFF-LVDS 20TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Buffer (Distribution), Multiplexerr
• Series: HiPerClockS™r

Specifications of ICS8543BGLF

• Number Of Circuits: 1
• Ratio - Input:output: 2:4
• Differential - Input:output: Yes/Yes
• Input: CML, HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVDS
• Frequency - Max: 800MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 800MHz
• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 800MHz
• Output Logic Level: LVDS
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1186; 800-1186-5; 800-1186; 8543BGLF

ICS8543 Data Sheet
Revision History Sheet
ICS8543BG REVISION E DECEMBER 17, 2010
Rev
A
A
A
A
B
C
D
D
D
D
E
E
Table
T4E
T5
4E
T2
T1
T8
T5
T9
6 - 10
Page
10
11
10
13
10
11
12
13
10
11
12
13
16
14
5
3
3
1
5
1
5
2
4
9
2
3
1
6
7
1
Description of Change
In the V
Updated Figure 1, CLK_EN Timing Diagram.
Updated Figure 1, CLK_EN Timing Diagram.
Features section, Bullet 6 to read 3.3V LVDS levels instead of LVPECL.
Updated Parameter Measurement Information figures.
AC Characteristics table - revised Output Frequency from 650MHz to 800MHz.
Features - deleted bullet "Designed to meet or exceed the requirements of
ANSI TIA/EIA-644".
LVDS Table - changed V
Pin Characteristics - changed C
Absolute Maximum Ratings - changed Output rating.
Added Differential Clock Input Interface section.
Added LVPECL Clock Input Interface section.
Added LVDS Driver Termination section.
Updated format throughout data sheet.
Pin Description table - added function description to the OE pin.
Updated LVPECL Clock Input Interface section.
Added Lead Free part number to Ordering Information table.
Updated Figure 1, CLK_EN Timing Diagram.
Updated Differential Clock Input Interface section.
Updated LVPECL Clock Input Interface section.
Added Recommendation for Unused Input and Output Pins section.
Added Power Considerations section.
Updated format throughout the datasheet.
Features section - added Additive Phase Jitter bullet.
AC Characteristics Table - added Added Phase Jitter spec and thermal note.
Added Additive Phase Jitter plot.
Updated Wiring the Differential Input to Accept Single-ended Levels section.
Updated 3.3V Differential Clock Input Interface section.
Updated 3.3V LVPECL Clock Input Interface section.
Updated LVDS Driver Termination section.
Ordering Information Table - deleted “ICS” prefix from Part/Order Number column.
Updated datasheet header/footer style.
Page 1, corrected Header Title.
Power Considerations - corrected typo for junction temperature from 827.7°C to 82.7°C.
OL
row, 1.06 has been moved to the Typical column from the maximum column.
OD
typical value from 350mV to 280mV.
IN
4pF max. to 4pF typical.
17
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
©2010 Integrated Device Technology, Inc.
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Date