ICS8543BGLF IDT, Integrated Device Technology Inc, ICS8543BGLF Datasheet - Page 3

• Manufacturer Part Number: ICS8543BGLF
• Description: IC FANOUT BUFF DIFF-LVDS 20TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Fanout Buffer (Distribution), Multiplexerr
• Series: HiPerClockS™r

Specifications of ICS8543BGLF

• Number Of Circuits: 1
• Ratio - Input:output: 2:4
• Differential - Input:output: Yes/Yes
• Input: CML, HCSL, LVDS, LVHSTL, LVPECL, SSTL
• Output: LVDS
• Frequency - Max: 800MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 20-TSSOP
• Frequency-max: 800MHz
• Number Of Clock Inputs: 2
• Mode Of Operation: Differential
• Output Frequency: 800MHz
• Output Logic Level: LVDS
• Operating Supply Voltage (min): 3.135V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Package Type: TSSOP
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 20
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 800-1186; 800-1186-5; 800-1186; 8543BGLF

ICS8543 Data Sheet
Function Tables
Table 3A. Control Input Function Table
After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge as shown in Figure 1.
In the active mode, the state of the outputs are a function of the CLK/nCLK and PCLK/nPCLK inputs as described in Table 3B.
Figure 1. CLK_EN Timing Diagram
Table 3B. Clock Input Function Table
NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels.
ICS8543BG REVISION E DECEMBER 17, 2010
nCLK, nPCLK
CLK, PCLK
Biased; NOTE 1
Biased; NOTE 1
nQ0:nQ3
CLK or PCLK
CLK_EN
Q0:Q3
OE
0
1
1
1
1
0
1
0
1
Inputs
nCLK or nPCLK
Biased; NOTE 1
Biased; NOTE 1
CLK_EN
X
0
0
1
1
1
0
0
1
Inputs
Disabled
CLK_SEL
Q[0:3]
HIGH
HIGH
HIGH
LOW
LOW
LOW
X
0
1
0
1
Outputs
nQ[0:3]
3
HIGH
HIGH
HIGH
LOW
LOW
LOW
Selected Source
PCLK, nPCLK
PCLK, nPCLK
CLK, nCLK
CLK, nCLK
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Single-Ended to Differential
Differential to Differential
Differential to Differential
Input to Output Mode
LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER
Disabled; Low
Disabled; Low
Enabled
Enabled
Q[0:3]
Hi-Z
Enabled
©2010 Integrated Device Technology, Inc.
Outputs
Disabled; High
Disabled; High
Non-Inverting
Non-Inverting
Non-Inverting
Non-Inverting
Inverting
Inverting
Enabled
Enabled
nQ[0:3]
Polarity
Hi-Z