ICS8543BGI IDT, Integrated Device Technology Inc, ICS8543BGI Datasheet
ICS8543BGI
Specifications of ICS8543BGI
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ICS8543BGI Summary of contents
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... Available in both standard (RoHS 5) and lead-free (RoHS 6) packages Pin Assignment CLK_EN CLK_SEL Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 6.5mm x 4.4mm x 0.925 1 ICS8543I GND nQ0 CLK nCLK 5 16 nQ1 PCLK nPCLK 7 14 nQ2 GND nQ3 DD ICS8543I 20-Lead TSSOP mm package body G Package Top View ICS8543BGI REV. E SEPTEMBER 9, 2008 ...
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... Q3/nQ3. LVCMOS/LVTTL interface levels. Positive supply pins. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Test Conditions 2 Minimum Typical Maximum ICS8543BGI REV. E SEPTEMBER 9, 2008 Units pF Ω k Ω k ...
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... Hi-Z Disabled; Low Disabled; High Disabled; Low Disabled; High Enabled Enabled Enabled Enabled Enabled Input to Output Mode Differential to Differential Non-Inverting Differential to Differential Non-Inverting Single-Ended to Differential Non-Inverting Single-Ended to Differential Non-Inverting Single-Ended to Differential Single-Ended to Differential ICS8543BGI REV. E SEPTEMBER 9, 2008 Hi-Z Polarity Inverting Inverting ...
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... DD A Test Conditions Minimum 3.135 = 3.3V ± 5 -40°C to 85° Test Conditions 3.465V 3.465V 3.465V 3.465V Typical Maximum 3.3 3.465 50 Minimum Typical Maximum 0.3 DD -0.3 0.8 5 150 -150 -5 ICS8543BGI REV. E SEPTEMBER 9, 2008 Units V mA Units V V µA µA µA µA ...
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... V DD Minimum Typical Maximum 200 280 360 0 40 1.125 1.25 1.375 5 25 -10 +10 -20 ±1 +20 -3.5 -5 -3.5 -5 1.34 1.6 0.9 1.06 ICS8543BGI REV. E SEPTEMBER 9, 2008 Units µA µA µA µ Units µA µA µA µ Units µA µ ...
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... IDT™ / ICS™ LVDS FANOUT BUFFER = 3.3V ± 5 -40°C to 85°C A Test Conditions 153.6MHz, Integration Range: 12kHz – 20MHz ƒ ≤ 650MHz 20% to 80% @ 50MHz odc 6 Minimum Typical Maximum 650 0.164 1.5 2.6 40 600 150 450 ICS8543BGI REV. E SEPTEMBER 9, 2008 Units MHz ...
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... Additive Phase Jitter @ 153.6MHz 12kHz to 20MHz = 0.164ps (typical) Offset from Carrier Frequency (Hz) device. This is illustrated above. The device meets the noise floor of what is shown, but can actually be lower. The phase noise is dependent on the input source and measurement equipment. 7 ICS8543BGI REV. E SEPTEMBER 9, 2008 ...
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... Part-to-Part Skew IDT™ / ICS™ LVDS FANOUT BUFFER V DD SCOPE Qx nCLK, nPCLK CLK, nQx PCLK GND Differential Input Level nQx Qx nQy Qy Output Skew nCLK, nPCLK CLK, PCLK nQ[0:3] Q[0:3] Propagation Delay Cross Points PP tsk( ICS8543BGI REV. E SEPTEMBER 9, 2008 CMR ...
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... Output Duty Cycle/Pulse Width/Period out ➤ DC Input out V /∆ Differential Output Voltage Setup out Input out I OZ Differential Output Short Circuit Setup PERIOD t PW odc = x 100% t PERIOD V DD LVDS 100 V DD LVDS ICS8543BGI REV. E SEPTEMBER 9, 2008 out ➤ V /∆ ➤ out out I OSD out ...
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... V = 3.3V, V_REF should be 1.25V and DD R2/R1 = 0.609. IDT™ / ICS™ LVDS FANOUT BUFFER out OSB out Power Off Leakage Setup / CLK_IN Figure 2. Single-Ended Signal Driving Differential Input 10 LVDS I OFF V_REF - C1 R2 0.1uF 1K ICS8543BGI REV. E SEPTEMBER 9, 2008 V DD ...
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... Zo = 50Ω R1 100 Zo = 50Ω LVDS Driven by a 3.3V LVDS Driver 2. 120 120 Zo = 60Ω 60Ω SSTL R1 R2 120 120 Driven by a 2.5V SSTL Driver ICS8543BGI REV. E SEPTEMBER 9, 2008 3.3V CLK nCLK HiPerClockS Input 3.3V CLK nCLK Receiver 3.3V CLK nCLK HiPerClockS ...
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... Zo = 50Ω 3.3V LVPECL 50Ω 100 - 200 100 - 200 125 a 3.3V LVPECL Driver with AC Couple Zo = 50Ω R1 100 Zo = 50Ω LVDS a 3.3V LVDS Driver ICS8543BGI REV. E SEPTEMBER 9, 2008 3.3V PCLK nPCLK HiPerClockS PCLK/nPCLK 3. PCLK nPCLK HiPerClockS PCLK/nPCLK R2 125 3.3V PCLK nPCLK ...
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... All unused LVDS output pairs can be either left floating or terminated with 100Ω across. If they are left floating, there should be no trace attached. For a multiple LVDS outputs buffer, if only partial outputs are used recommended to terminate the unused outputs. 50Ω 100Ω – 50Ω 13 3.3V ICS8543BGI REV. E SEPTEMBER 9, 2008 ...
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... IDT™ / ICS™ LVDS FANOUT BUFFER = 3. 3.465V, which gives worst case results 3.465V * 50mA = 173.25mW DD_MAX * Pd_total + θ by Velocity JA 0 114.5°C/W 73.2°C/W 14 must be used. Assuming no air flow JA 200 500 98.0°C/W 88.0°C/W 66.6°C/W 63.5°C/W ICS8543BGI REV. E SEPTEMBER 9, 2008 ...
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... Symbol Minimum 0.05 A2 0.80 b 0.19 c 0.09 D 6.40 E 6.40 Basic E1 4.30 e 0.65 Basic L 0.45 α 0° aaa Reference Document: JEDEC Publication 95, MO-153 15 500 88.0°C/W 63.5°C/W Maximum 1.20 0.15 1.05 0.30 0.20 6.60 4.50 0.75 8° 0.10 ICS8543BGI REV. E SEPTEMBER 9, 2008 ...
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... Shipping Packaging 20 Lead TSSOP 20 Lead TSSOP 2500 Tape & Reel “Lead-Free” 20 Lead TSSOP “Lead-Free” 20 Lead TSSOP 2500 Tape & Reel 16 Temperature Tube -40°C to 85°C -40°C to 85°C Tube -40°C to 85°C -40°C to 85°C ICS8543BGI REV. E SEPTEMBER 9, 2008 ...
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... Added Additive Phase Jitter Plot. 9 Parameter Measurement Information - updated Output Rise/Fall Time diagram. IDT™ / ICS™ LVDS FANOUT BUFFER typical value from 350mV to 280mV. OD 4pF max. to 4pF typical 0.3V. 17 Date 10/17/01 11/2/01 5/6/02 9/19/02 1/5/04 max. from 2/27/08 9/9/08 ICS8543BGI REV. E SEPTEMBER 9, 2008 ...
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ICS8543I LOW SKEW, 1-TO-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Contact Information: www.IDT.com Sales 800-345-7015 (inside USA) +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT © 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT ...