ICS8543BG IDT, Integrated Device Technology Inc, ICS8543BG Datasheet
ICS8543BG
Specifications of ICS8543BG
Available stocks
Related parts for ICS8543BG
ICS8543BG Summary of contents
Page 1
... Pullup nPCLK Pulldown CLK_SEL Pullup OE ICS8543BG REVISION E DECEMBER 17, 2010 Features • Four differential LVDS output pairs • Selectable differential CLK, nCLK or LVPECL clock inputs • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • ...
Page 2
... IN R Input Pullup Resistor PULLUP R Input Pulldown Resistor PULLDOWN ICS8543BG REVISION E DECEMBER 17, 2010 Type Description Power supply ground. Synchronizing clock enable. When HIGH, clock outputs follows clock input. When Pullup LOW, Qx outputs are forced low, nQx outputs are forced high. LVCMOS / LVTTL interface levels. ...
Page 3
... Biased; NOTE 1 1 Biased; NOTE 1 Biased; NOTE 1 0 Biased; NOTE 1 1 NOTE 1: Please refer to the Application Information section, Wiring the Differential Input to Accept Single-Ended Levels. ICS8543BG REVISION E DECEMBER 17, 2010 Inputs CLK_SEL Selected Source X 0 CLK, nCLK 1 PCLK, nPCLK 0 CLK, nCLK ...
Page 4
... Input High Voltage IH V Input Low Voltage IL OE, CLK_EN I Input High Current IH CLK_SEL OE, CLK_EN I Input Low Current IL CLK_SEL ICS8543BG REVISION E DECEMBER 17, 2010 Rating 4.6V -0. 0.5V DD 10mA 15mA 73.2°C/W (0 lfpm) -65°C to 150°C = 3.3V ± 5 0°C to 70° Test Conditions Minimum 3 ...
Page 5
... OS I High Impedance Leakage Oz Power Off Leakage I OFF I Differential Output Short Circuit Current OSD I Output Short Circuit Current OS V Output Voltage High OH V Output Voltage Low OL ICS8543BG REVISION E DECEMBER 17, 2010 = 3.3V ± 5 0°C to 70° Test Conditions 3.465V 3.465V 3.465V ...
Page 6
... NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. ICS8543BG REVISION E DECEMBER 17, 2010 = 3.3V ± 5 0°C to 70°C ...
Page 7
... As with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This ICS8543BG REVISION E DECEMBER 17, 2010 LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER of the power in the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental ...
Page 8
... LVDS Output Load AC Test Circuit V DD nQ[0:3] V Cross Points OD Q[0: GND Differential Output Level Par t 1 nQx Qx Par t 2 nQy Qy tsk(pp) Part-to-Part Skew ICS8543BG REVISION E DECEMBER 17, 2010 V DD SCOPE Qx nCLK, nPCLK CLK, nQx PCLK GND Differential Input Level nQx Qx nQy Qy Output Skew nCLK, nPCLK CLK, ...
Page 9
... R Output Rise/Fall Time V DD LVDS DC Input ➤ Offset Voltage Setup 3.3V±5% POWER SUPPLY LVDS t _ Float GND DC Inpu + High Impedance Leakage Current Setup ICS8543BG REVISION E DECEMBER 17, 2010 80 20 Output Duty Cycle/Pulse Width/Period out ➤ DC Input out V /∆ Differential Output Voltage Setup ...
Page 10
... In addition, matched termination at the input will attenuate the signal in half. This can be done in one of two ways. First, R3 and R4 in parallel should equal the transmission Figure 1. Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels ICS8543BG REVISION E DECEMBER 17, 2010 out I OS ...
Page 11
... HCSL *Optional – R3 and R4 can be 0Ω Figure 3E. CLK/nCLK Input Driven by a 3.3V HCSL Driver ICS8543BG REVISION E DECEMBER 17, 2010 Please consult with the vendor of the driver component to confirm the and V must meet the V driver termination requirements. For example, in Figure 3A, the input ...
Page 12
... Zo = 60Ω 60Ω SSTL R1 120 Figure 4E. PCLK/nPCLK Input Driven by a 2.5V SSTL Driver ICS8543BG REVISION E DECEMBER 17, 2010 The input interfaces suggested here are examples only. If the driver must meet the V and is from another vendor, use their termination recommendation Please consult with the vendor of the driver component to confirm the driver termination requirements ...
Page 13
... The standard LVDS Driver 100Ω Differential Transmission Line Figure 5. Typical LVDS Driver Termination ICS8543BG REVISION E DECEMBER 17, 2010 LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER Outputs: LVDS Outputs All unused LVDS outputs should be terminated with 100Ω resistor between the differential pair ...
Page 14
... Table 6. Thermal Resitance for 20 Lead TSSOP, Forced Convection JA Linear Feet per Minute Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards ICS8543BG REVISION E DECEMBER 17, 2010 = 3. 3.465V, which gives worst case results 3.465V * 50mA = 173.25mW DD_MAX * Pd_total + θ ...
Page 15
... Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ICS8543 is: 636 Package Outline and Package Dimensions Package Outline - G Suffix for 20 Lead TSSOP ICS8543BG REVISION E DECEMBER 17, 2010 LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER θ by Velocity JA 0 200 114.5° ...
Page 16
... IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. ICS8543BG REVISION E DECEMBER 17, 2010 LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER ...
Page 17
... Page 1, corrected Header Title Power Considerations - corrected typo for junction temperature from 827.7°C to 82.7°C. ICS8543BG REVISION E DECEMBER 17, 2010 row, 1.06 has been moved to the Typical column from the maximum column. OL typical value from 350mV to 280mV. OD 4pF max. to 4pF typical. ...
Page 18
ICS8543 Data Sheet We’ve Got Your Timing Solution 6024 Silver Creek Valley Road Sales 800-345-7015 (inside USA) San Jose, California 95138 +408-284-8200 (outside USA) Fax: 408-284-2775 www.IDT.com/go/contactIDT DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to ...