ICS950812CGLFT IDT, Integrated Device Technology Inc, ICS950812CGLFT Datasheet - Page 26

• Manufacturer Part Number: ICS950812CGLFT
• Description: IC FREQ GEN 200MHZ CLK 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Frequency Generatorr

Specifications of ICS950812CGLFT

• Input: Crystal
• Output: Clock
• Frequency - Max: 200MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 950812CGLFT

IDT
ICS950812
Frequency Generator with 200MHz Differential CPU Clocks
TM
CPU_STOP# - De-assertion (transition from logic "0" to logic "1")
Frequency Generator with 200MHz Differential CPU Clocks
All CPU outputs that were stopped are to resume normal operation in a glitch free manner. The maximum latency from the de-
assertion to active outputs is to be defined to be between 2 - 6 CPU clock periods (2 clocks are shown). If the I2C Bit 6 of Byte
1 is programmed to "1" then the stopped CPU outputs will be driven High within 10 nS of CPU_Stop# de-assertion.
PD# - Assertion (transition from logic "1" to logic "0")
When PWRDWN# is sampled low by two consecutive rising edges of CPU clock, then all clock outputs except CPU clocks
must be held low on their next high to low transitions. When the I2C Bit 6 of Byte 0 is programmed to '0' CPU clocks must be
held with the CPU clock pin driven high with a value of 2 x Iref, and CPU# undriven. If Bit 6 of Byte 0 is '1' then both CPU and
CPU# are undriven. Note the example below shows CPU = 133 MHz and Bit 6 of Byte 0 = '0', this diagram and description is
applicable for all valid CPU frequencies 66, 100, 133, 200 MHz.
Due to the state if the internal logic, stopping and holding the REF clock outputs in the LOW state may require more than one
clock cycle to complete.
PD# Functionality
*CPUCLKT(2:0)TS
CPUCLKC(2:0)
CPUCLKT(2:0)
P
CPU_STOP#
D
0
1
#
CPUCLKT 100MHz
CPUCLKC 100MHz
REF 14.318MHz
PCICLK 33MHz
C
66MHz_OUT
USB 48MHz
i
e r
P
N
66MHz_IN
3V66MHz
* f
U
r o
C
m
M
L
PD#
l a
K
u
t l
*Signal TS is CPUCLKT in Tri-State mode
T
0ns
C
P
N
Tdrive_CPU_STOP# <10ns @ 200mV
F
U
r o
o l
C
m
De-assertion of CPU_STOP# Waveforms
t a
L
Power Down Assertion of Waveforms
l a
K
C
6
3
6
L
V
M
o
6
w
H
6
z
25ns
26
6
6
6
M
6
M
H
L
H
o
z
w
_
z
O
_
N I
U
T
6
P
6
P
C
M
C
C I
L
50ns
H
C I
o
z
L
w
_
L
K
N I
K
_
2 /
F
6
6
P
M
C
L
H
C I
o
z
w
_
L
N I
K
2 /
U
0542J—01/25/10
4
4
S
8
8
L
B
M
M
o
D /
w
H
H
O
z
z
T