ICS950812CGLFT IDT, Integrated Device Technology Inc, ICS950812CGLFT Datasheet - Page 25

• Manufacturer Part Number: ICS950812CGLFT
• Description: IC FREQ GEN 200MHZ CLK 56-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Frequency Generatorr

Specifications of ICS950812CGLFT

• Input: Crystal
• Output: Clock
• Frequency - Max: 200MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Frequency-max: 200MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 950812CGLFT

IDT
ICS950812
Frequency Generator with 200MHz Differential CPU Clocks
TM
Frequency Generator with 200MHz Differential CPU Clocks
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the PCI_STOP# signal will be the following. All PCI[6:0] and stoppable PCI_F[2,0] clocks will latch low
in their next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising
edge.
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I
assertion of CPU_STOP# are to be stopped after their next transition. When the I
state of the stopped CPU signals is CPU = High and CPU# = Low. There is to be no change to the output drive current values.
The CPU will be driven high with a current value equal to (Mult 0 'select') x (Iref), the CPU# signal will not be driven . When the
I
be driven.
CPU_STOP# Functionality
2
C Bit 6 of Byte 1 is programmed to '1' then final state of the stopped CPU signals is Low, both CPU and CPU# outputs will not
C
P
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0
1
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O
CPU_STOP#
P
#
CPUCLKC
CPUCLKT
PCI_F[2:0] 33MHz
PCI[6:0] 33MHz
PCI_STOP#
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N
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Assertion of CPU_STOP# Waveforms
Assertion of PCI_STOP# Waveforms
tsu
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P
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m
25
t a
C
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2
C Bit 6 of Byte 1 is programmed to '0' the final
2
C configuration to be stoppable via
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