ICS9DB423BGLFT IDT, Integrated Device Technology Inc, ICS9DB423BGLFT Datasheet

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ICS9DB423BGLFT

Manufacturer Part Number
ICS9DB423BGLFT
Description
IC PC CLOCK 3.3V 28-TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Clock Bufferr
Datasheet

Specifications of ICS9DB423BGLFT

Input
Clock
Output
Clock
Frequency - Max
400MHz
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
28-TSSOP
Frequency-max
400MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
9DB423BGLFT
Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
Recommended Application:
DB400Q compatible part with PCIe Gen1, Gen 2 and QPI
support
General Description:
The ICS9DB423 is compatible with the Intel DB400Q Differential
Buffer Specification. This buffer provides 4 PCI-Express SRC or
4 QPI clocks. The ICS9DB423 is driven by a differential output
pair from a CK410B+ or CK509B main clock generator.
Key Specifications
Functional Block Diagram
Note: Polarities shown for OE_INV = 0.
IDT
®
Output cycle-cycle jitter < 50ps.
Output to Output skew <50ps
Phase jitter: PCIe Gen1 < 86ps peak to peak
Phase jitter: PCIe Gen2 < 3.0/3.1ps rms
Phase jitter: QPI < 0.5ps rms
RoHS compliant packaging
Four Output Differential Buffer for PCIe and Gen 1, Gen 2 and QPI
OE(6,1)
SRC_IN
SRC_IN#
PD
BYPASS#_133_100
HIGH_BW#
DIF_STOP#
SDATA
SCLK
2
CONTROL
LOGIC
COMPATIBLE
SPREAD
PLL
1
Features/Benefits
Output Features
M
U
X
4 - 0.7V current-mode differential output pairs
Supports zero delay buffer mode and fanout mode
Bandwidth programming available
50-133 MHz operation in PLL mode
33-400 MHz operation in Bypass mode
Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread.
Supports undriven differential outputs in Power Down and
DIF_STOP# modes for power management.
LOGIC
STOP
4
IREF
DIF(6,5,2,1)
1437 Rev C - 01/27/11
9DB423B
DATASHEET

Related parts for ICS9DB423BGLFT

ICS9DB423BGLFT Summary of contents

Page 1

Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI Recommended Application: DB400Q compatible part with PCIe Gen1, Gen 2 and QPI support General Description: The ICS9DB423 is compatible with the Intel DB400Q Differential Buffer Specification. This buffer ...

Page 2

Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI Pin Configuration VDD 1 SRC_IN 2 SRC_IN# 3 GND 4 VDD 5 DIF_1 6 DIF_1# 7 OE_1 8 DIF_2 9 DIF_2# 10 VDD 11 BYPASS#_133_100 12 ...

Page 3

Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI Pin Description for OE_INV = 0 PIN # PIN NAME PIN TYPE 1 VDD PWR 2 SRC_IN IN 3 SRC_IN GND PWR 5 VDD ...

Page 4

Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI Pin Description for OE_INV = 1 PIN # PIN NAME PIN TYPE 1 VDD PWR 2 SRC_IN IN 3 SRC_IN GND PWR 5 VDD ...

Page 5

Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI Absolute Max Symbol Parameter VDD_A 3.3V Core Supply Voltage VDD_In 3.3V Logic Supply Voltage V Input Low Voltage IL V Input High Voltage IH Ts Storage ...

Page 6

Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI Electrical Characteristics - Clock Input Parameters 70°C; Supply Voltage V = 3.3 V +/- PARAMETER SYMBOL Input High Voltage - ...

Page 7

Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI Electrical Characteristics - DIF 0.7V Current Mode Differential Pair 70° 3.3 V +/-5 PARAMETER SYMBOL Current Source ...

Page 8

Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI Clock Periods Differential Outputs with Spread Spectrum Enabled Measurement Window 1 Clock Symbol Lg- -SSC Absolute Short-term Period Average Definition Minimum Minimum Absolute Absolute Period Period ...

Page 9

Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI Common Recommendations for Differential Routing L1 length, route as non-coupled 50ohm trace L2 length, route as non-coupled 50ohm trace L3 length, route as non-coupled 50ohm trace ...

Page 10

Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI Alternative Termination for LVDS and other Common Differential Signals (figure 3) Vdiff Vp-p Vcm 0.45v 0.22v 1.08 0.58 0.28 0.6 0.80 0.40 0.6 0.60 0.3 1.2 ...

Page 11

Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI General SMBus serial interface information for the 9DB423B How to Write: • Controller (host) sends a start bit. • Controller (host) sends the write address DC ...

Page 12

Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (DC/DD) Byte 0 Pin # Name Bit 7 - PD_Mode Bit 6 - STOP_Mode Bit 5 - PD_Polarity Bit ...

Page 13

Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI SMBus Table: Vendor & Revision ID Register Byte 4 Pin # Name Bit 7 - RID3 Bit 6 - RID2 Bit 5 - RID1 Bit 4 ...

Page 14

Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI Note: Polarities in timing diagrams are shown OE_INV = 0. They are similar to OE_INV = 1. PD#, Power Down The PD# pin cleanly shuts off ...

Page 15

Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI DIF_STOP# The DIF_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must be present on SRC_IN for ...

Page 16

Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI DIF_STOP_3 (Stop_Mode = Driven, PD_Mode = Tristate) DIF_Stop# PWRDWN# DIF (Free Running) DIF# (Free Running) DIF (Stoppable) DIF# (Stoppable) DIF_STOP_4 (Stop_Mode = Tristate, PD_Mode = Tristate) ...

Page 17

Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI 209 mil SSOP Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI IDT ® 209 mil SSOP In Millimeters SYMBOL COMMON DIMENSIONS MIN ...

Page 18

Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI N E1 INDEX INDEX AREA AREA Ordering Information Part / Order Number Shipping Packaging 9DB423BFLF 9DB423BFLFT ...

Page 19

Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI Revision History Rev. Issue Date Description 1. Updated Electrical Characteristics to add propagation delay and phase noise information. 2. Corrected SMBus to reference pin numbers for 423 ...

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