ICS9DB423BGLFT IDT, Integrated Device Technology Inc, ICS9DB423BGLFT Datasheet - Page 3

• Manufacturer Part Number: ICS9DB423BGLFT
• Description: IC PC CLOCK 3.3V 28-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Bufferr

Specifications of ICS9DB423BGLFT

• Input: Clock
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9DB423BGLFT

Pin Description for OE_INV = 0
IDT
PIN #
9DB423B
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
®
1
2
3
4
5
6
7
8
9
Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
VDD
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
OE_1
DIF_2
DIF_2#
VDD
BYPASS#_133_100
SCLK
SDATA
PD#
DIF_STOP#
HIGH_BW#
VDD
DIF_5#
DIF_5
OE_6
DIF_6#
DIF_6
VDD
OE_INV
IREF
GNDA
VDDA
PIN NAME
PIN TYPE
PWR
PWR
PWR
PWR
PWR
PWR
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Power supply, nominal 3.3V
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
Active high input for enabling output 1.
0 =disable outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Input to select Bypass(fan-out), QPI PLL (133MHz) or PCIe PLL (100MHz) mode
0 = Bypass mode, M= QPI, 1= PCIe PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Asynchronous active low input pin used to power down the device. The internal
clocks are disabled and the VCO and the crystal osc. (if any) are stopped.
Active low input to stop differential output clocks.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Active high input for enabling output 6.
0 =disable outputs, 1= enable outputs
0.7V differential Complementary clock output
0.7V differential true clock output
Power supply, nominal 3.3V
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
This pin establishes the reference for the differential current-mode output pairs. It
requires a fixed precision resistor to ground. 475ohm is the standard value for
100ohm differential impedance. Other impedances require different values. See data
sheet.
Ground pin for the PLL core.
3.3V power for the PLL core.
3
DESCRIPTION
1437 Rev C - 01/27/11