ICS9DB423BGLFT IDT, Integrated Device Technology Inc, ICS9DB423BGLFT Datasheet - Page 5

• Manufacturer Part Number: ICS9DB423BGLFT
• Description: IC PC CLOCK 3.3V 28-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Bufferr

Specifications of ICS9DB423BGLFT

• Input: Clock
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9DB423BGLFT

Absolute Max
Electrical Characteristics - Input/Supply/Common Output Parameters
IDT
T
1
2
3
4
5
SMBus Operating Frequency
Guaranteed by design and characterization, not 100% tested in production.
See timing diagrams for timing requirements.
Time from deassertion until outputs are >200 mV
SRC_IN input
The differential input clock must be running for the SMBus to be active
A
Operating Supply Current
9DB423B
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
Low-level Output Voltage
= 0 - 70°C; Supply Voltage V
®
Tambient
Current sinking at V
Clock/Data Rise Time
Clock/Data Fall Time
ESD prot
Input SS Modulation
Symbol
VDD_In
Powerdown Current
Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
VDD_A
Tcase
Input High Voltage
PLL Jitter Peaking
Input Low Voltage
Input High Current
Tdrive_DIF_Stop#
Input Low Current
Input Frequency
Clk Stabilization
V
Pin Inductance
PLL Bandwidth
SMBus Voltage
V
Ts
PARAMETER
SCLK/SDATA
SCLK/SDATA
OE# Latency
Capacitance
Tdrive_PD#
IH
IL
Frequency
Trise
Tfall
OL
3.3V Logic Supply Voltage
3.3V Core Supply Voltage
Ambient Operating Temp
SYMBOL
C
DD
F
I
I
f
Storage Temperature
Input ESD protection
t
t
I
DD3.3OP
t
DD3.3PD
INSRC_IN
t
f
MAXSMB
iBYPASS
T
LATOE#
DRVSTP
PULLUP
t
human body model
F
F
C
DRVPD
V
t
JPEAK
MODIN
Input High Voltage
Case Temperature
Input Low Voltage
BW
V
RSMB
V
L
C
FSMB
= 3.3 V +/-5%
V
I
I
STAB
I
iPLL
iPLL
t
IL1
IL2
OUT
t
MAX
IH
pin
R
OL
IH
IN
F
IL
Parameter
stabilization or de-assertion of PD# to 1st clock
V
From V
IN
V
Maximum SMBus operating frequency
Bypass Mode (Bypass/133/100= 0)
IN
= 0 V; Inputs with no pull-up resistors
PCIe Mode (Bypass/133/100= 1)
Rise time of PD# and DIF_Stop#
QPI Mode (Bypass/133/100= M)
SRC_IN differential clock inputs
Fall time of PD# and DIF_Stop#
DIF stop after OE# deassertion
= 0 V; Inputs with pull-up resistors
Logic Inputs, except SRC_IN
DIF start after OE# assertion
all differential pairs tri-stated
-3dB point in High BW Mode
-3dB point in Low BW Mode
Full Active, C
DD
DIF_Stop# de-assertion
Output pin capacitance
Maximum input voltage
(Triangular Modulation)
DIF output enable after
DIF output enable after
Peak Pass band Gain
Allowable Frequency
Power-Up and after input clock
(Min VIH + 0.15) to
(Max VIL - 0.15) to
all diff pairs driven
PD# de-assertion
(Min VIH + 0.15)
(Max VIL - 0.15)
CONDITIONS
3.3 V +/-5%
3.3 V +/-5%
V
@ I
IN
PULLUP
= V
L
= Full load;
DD
GND-0.5
2000
Min
-65
0
5
V
DD
Max
150
115
4.6
4.6
+0.5V
70
GND - 0.3
MIN
-200
1.5
1.5
0.7
50
67
33
30
-5
-5
2
2
1
4
Units
°
°C
°C
V
V
V
V
V
C
100.00
133.33
TYP
1.5
3
1
V
DD
MAX
1000
200
110
140
400
300
300
100
0.8
2.7
1.4
5.5
0.4
60
33
10
5
6
7
5
6
4
2
1
3
5
5
+ 0.3
UNITS NOTES
cycles
MHz
MHz
MHz
MHz
MHz
kHz
kHz
mA
mA
mA
ms
mA
uA
uA
uA
nH
dB
pF
pF
pF
ns
us
ns
ns
ns
ns
V
V
V
V
1437 Rev C - 01/27/11
1,4
1,2
1,3
1,3
1,3
1,5
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1