ICS9DB423BGLFT IDT, Integrated Device Technology Inc, ICS9DB423BGLFT Datasheet - Page 7

• Manufacturer Part Number: ICS9DB423BGLFT
• Description: IC PC CLOCK 3.3V 28-TSSOP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Clock Bufferr

Specifications of ICS9DB423BGLFT

• Input: Clock
• Output: Clock
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 9DB423BGLFT

IDT
1
2
4
5
6
7
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
T
3 Measured from differential waveform
Guaranteed by design and characterization, not 100% tested in production.
I
A
See http://www.pcisig.com for complete specs
Device driven by 932S421C or equivalent.
6.4Gb 12UI
First number is High Bandwidth Mode, second number is Low Bandwidth Mode
REF
9DB423B
Four Output Differential Buffer for PCIe for Gen 1, Gen 2 and QPI
Skew, Output to Output
®
Current Source Output
Crossing Voltage (abs)
Crossing Voltage (var)
= 0 - 70°C; V
Skew, Input to Output
Jitter, Cycle to cycle
Rise Time Variation
Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI
Fall Time Variation
= V
PARAMETER
Voltage High
Jitter, Phase
Voltage Low
Max Voltage
Min Voltage
Impedance
Duty Cycle
DD
Rise Time
Fall Time
/(3xR
DD
R
). For R
= 3.3 V +/-5%; C
R
= 475Ω (1%), I
Vcross(abs)
SYMBOL
d-Vcross
t
t
jphaseBYP
jphasePLL
VHigh
VLow
t
t
Vuds
Vovs
t
jcyc-cyc
pdBYP
pdPLL
Zo
d-t
d-t
t
d
sk3
t
t
L
t3
r
f
1
r
f
=2pF, R
REF
Measurement on single ended signal using
Statistical measurement on single ended
Measurement from differential wavefrom
S
signal using oscilloscope math function.
=33Ω, R
= 2.32mA. I
Variation of crossing over all edges
PCIe Gen 2 High Band phase jitter
PCIe Gen 2 High Band phase jitter
PCIe Gen 2 Low Band phase jitter
PCIe Gen 2 Low Band phase jitter
Additive Jitter in Bypass Mode
V
V
(Additive in Bypass Mode)
(Additive in Bypass Mode)
(Additive in Bypass Mode)
(Additive in Bypass Mode)
OL
Bypass Mode, V
OH
PCIe Gen 1 phase jitter
PCIe Gen1 phase jitter
P
PLL Mode V
= 0.175V, V
=49.9Ω, R
= 0.525V V
QPI phase jitter
QPI phase jitter
absolute value.
CONDITIONS
OH
PLL mode
V
= 6 x I
T
= 50%
7
REF
T
REF
OH
OL
= 50%
=475Ω
T
= 0.175V
= 0.525V
= 50%
and V
OH
= 0.7V @ Z
3000
2500
-150
-300
-250
MIN
660
250
175
175
45
O
=50Ω.
TYP
0.28
2.7/
0.7
1.5
2.2
37
7
0
1150
4500
MAX
0.16
850
150
550
140
700
700
125
125
250
0.1
0.9
3.1
0.5
55
50
50
50
10
86
3
1437 Rev C - 01/27/11
(pk2pk)
(pk2pk)
UNITS NOTES
(rms)
(rms)
(rms)
(rms)
(rms)
(rms)
mV
mV
mV
mV
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
%
Ω
1,4,5,7
1,4,5
1,4,5
1,4,5
1,5,6
1,4,5
1,4,5
1,5,6
1,2
1,2
1,3
1,3
1
1
1
1
1
1
1
1
1
1
1
1
1